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Ketan Contact options for registered users 's Avatar (by Gravatar) posted on
July 5, 2003, 5:30 am
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hello there
i am relatively new to VHDL..this might sound simple
any ideas how to carry out division (floating point) in VHDL??

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Replace_latter8717_with_manorsway Contact options for registered users 's Avatar (by Gravatar) posted on
July 6, 2003, 7:52 pm
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Re: division
remember log division from schoool, now try that in base 2!


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Mario Trams Contact options for registered users 's Avatar (by Gravatar) posted on
July 6, 2003, 10:28 pm
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Re: division

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Yes.
And then develop a hardware design that can do that...

When this is done, it's a small step to describe it in VHDL.

Regards,
Mario

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Replace_latter8717_with_manorsway Contact options for registered users 's Avatar (by Gravatar) posted on
July 9, 2003, 8:31 pm
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Re: division
Sorry I meant LONG division not LOG

hope this helps

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Glen Herrmannsfeldt Contact options for registered users 's Avatar (by Gravatar) posted on
July 9, 2003, 11:09 pm
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Re: division

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For a few seconds I considered that you meant subtracting logs to do
division.  But then I figured it out.  I don't think subtracting logs and
then antilog is likely to be a very good way in FPGA.

-- glen



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Peter Alfke Contact options for registered users 's Avatar (by Gravatar) posted on
July 10, 2003, 12:28 am
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Re: division
In the 'sixties, the Wang calculators ( with Nixie-tube read-out) did
just that. I think they used a very efficient algorithm for log and antilog
Peter Alfke
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Glen Herrmannsfeldt wrote:
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