division

hello there i am relatively new to VHDL..this might sound simple any ideas how to carry out division (floating point) in VHDL??

Reply to
Ketan
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remember log division from schoool, now try that in base 2!

Reply to
Replace_latter8717_with_manorsway

Yes. And then develop a hardware design that can do that...

When this is done, it's a small step to describe it in VHDL.

Regards, Mario

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---------------------------------------------------------------------- Digital Force / Mario Trams snipped-for-privacy@informatik.tu-chemnitz.de snipped-for-privacy@wooden-technology.de Chemnitz University of Technology

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Reply to
Mario Trams

Sorry I meant LONG division not LOG

h>

Reply to
Replace_latter8717_with_manorsway

For a few seconds I considered that you meant subtracting logs to do division. But then I figured it out. I don't think subtracting logs and then antilog is likely to be a very good way in FPGA.

-- glen

Reply to
Glen Herrmannsfeldt

Reply to
Peter Alfke

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