Re: Starter Question and Opinion on VHDL

A follow up:

Someone sent this solution to me and said it would provide no assymetrical
delays and would be better than a long elsif chain. Does anyone else have
any experience with this? It seems to me that a good fitter would render the
same solution.

Hi,

A clean way of doing this is:

CASE fastclkcnt IS
     WHEN 2 =>
                mrasnext <= '0';
                mcasnext <= '1';
                mwenext  <= '0';
                mdqmnext <= '1';
     WHEN 4 =>
                mrasnext <= '0';
                mcasnext <= '1';
                mwenext  <= '0';
                mdqmnext <= '1';
     WHEN 12 =>
                mrasnext <= '0';
                mcasnext <= '1';
                mwenext  <= '0';
                mdqmnext <= '1';
    WHEN OTHERS =>
END CASE;

like this you make a decoder-mux arrangement
equal to all signals, so no strugle with assimetric
delays. (a long elseif chain is not a good solution).