Re: Starter Question and Opinion on VHDL

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A follow up:

Someone sent this solution to me and said it would provide no assymetrical
delays and would be better than a long elsif chain. Does anyone else have
any experience with this? It seems to me that a good fitter would render the
same solution.


A clean way of doing this is:

CASE fastclkcnt IS
     WHEN 2 =>
                mrasnext <= '0';
                mcasnext <= '1';
                mwenext  <= '0';
                mdqmnext <= '1';
     WHEN 4 =>
                mrasnext <= '0';
                mcasnext <= '1';
                mwenext  <= '0';
                mdqmnext <= '1';
     WHEN 12 =>
                mrasnext <= '0';
                mcasnext <= '1';
                mwenext  <= '0';
                mdqmnext <= '1';

like this you make a decoder-mux arrangement
equal to all signals, so no strugle with assimetric
delays. (a long elseif chain is not a good solution).

Re: Starter Question and Opinion on VHDL

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"Better" is a style choice.  The "assymetrical delays" (sic) is a
canard caused by the respondent's lack of understanding of VHDL
signal assignment, I suspect.  The meaning of the VHDL is the
same in both cases.  As you say, a good synthesis tool should
give the same results for both (it's not really a "fitter"
Finally, any design that relies on symmetry of delay through
synthesised asynchronous logic deserves to fail.
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
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