A follow up:
Someone sent this solution to me and said it would provide no assymetrical delays and would be better than a long elsif chain. Does anyone else have any experience with this? It seems to me that a good fitter would render the same solution.
Hi,
A clean way of doing this is:
CASE fastclkcnt IS WHEN 2 =>
mrasnext
"Better" is a style choice. The "assymetrical delays" (sic) is a canard caused by the respondent's lack of understanding of VHDL signal assignment, I suspect. The meaning of the VHDL is the same in both cases. As you say, a good synthesis tool should give the same results for both (it's not really a "fitter" problem). Finally, any design that relies on symmetry of delay through synthesised asynchronous logic deserves to fail.
-- Jonathan Bromley, Consultant
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