Hi,
> I'm a student in computer science and I'm working on the Singular Value
> Decomposition. I have implementd the Brent Luk Van Loan SVD systolic array
> using HandelC on FPGA and I'm looking for existing FPGA or VLSI
> implementations to compare with.
> Does anyone know about hardware implementaions of the SVD ?
Doing floating point in an FPGA is pretty expensive (in terms of CLBs used). I do wonder how big your array is?
-- glen