Digital clock synthesis

Hal Murray · 2004-12-15T21:18:31+00:00

This is leftover from a couple of discussions a week or two ago.There is something interesting that I don't understand.In general, if I have an input clock and I want to generatean output clock, and the output clock is (much) slower thanthe input clock, I can do that with a FSM.The jitter on the output clock can be up to 1/2 of the inputclock off. (If it's off more, move it over by one.) If youare lucky and the numbers work out exactly, you get no jitter.(For example, dividing by 4.)But how close is the frequency? The output frequency is out = in * X / YY is the number of states in the FSM.Some combinations of X and Y give a better match to thetarget frequency. I'm pretty sure a math wizard would usecontinued fractions to explain it.I know how to implement this if Y is a power of 2. That'sjust an adder and it generally fits well into FPGA. Givena minute or 3, I can work out the value of the constant toadd.It's easy to get closer to the target frequency by using morebits in the adder. If the bottom bit of the constant isn't a1, then the adder will skip 1/2 (or 3/4 or..) of the states.So there are sweet spots where the bottom bit of the constantis a 1. This approach is also convenient if you want to make a sine wave rather than a square wave since you can feed the top N bits of the adder to a ROM lookup table.But powers of 2 may not work as well as some simple pairsof X and Y. Is there a simple implementation techniquefor arbitrary Y that fits well into FPGAs? Is it somethingas simple as use an adder and reset it back to 0 after Ysteps?Is there a good web page or book that covers this area?Next step is to understand the spectrum of the synthesisedclock.-- The mail server is located in California. So are all myother mailboxes. Please do not send unsolicited bulk e-mail or unsolicitedcommercial e-mail to my address or any of my other addresses.These are my opinions, not necessarily my employer's. I hate spam.

Dec 15, 2004 23 Replies

Rate this thread:

John_H 21 years ago

bit?

You can have either a separate adder or (as I did it before) two different phase values supplied by software: the raw phase and the adjusted phase. If you want an adder to calculate the adjusted phase value, register the value and the timing doesn't suffer.

Just a reminder that the duty cycle will be (2^26/100M)/(1-2^26/100M) or

67.1%/32.9% on average unless you'd care to adjust whenever the MSbit toggles.

Vote

Falk Brunner 21 years ago

"Symon" schrieb im Newsbeitrag news: snipped-for-privacy@individual.net...

Why not use a xtal with a power of two frequency?? We telecom guys do this regulary.

Regards Falk

Vote

RobJ 21 years ago

Ray -

I agree for a general-purpose synthesizer with a phase accumulator addressing a SINE look-up table. But if you don't need a general-purpose synthesizer (i.e., you only need to generate one output frequency) then can't you pick any modulus you need and create the SINE LUT to match that modulus?

And if you just need a digital (1-bit) output clock then you should always be able to pick whatever accumulator modulus you want and use the MS bit of the accumulator as the output clock. The only requirements are that Fout = Fin * (M/N), where M and N are both integers and M/N

Vote

james 21 years ago

*********

Unless you are dealing with an application that needs a frequency tolerance of +/- less than 1 Hertz, a 27 bit accumalator and a 100 MHz clock is quite fine. It is rare in consumer or most industrial electronics that the frequency generated need be that tight of tolerance. Even if so then pick a value for your accumalator and match the crystal that will give you 1 Hz steps.

james

Vote

Join the Discussion

Have something to add? Share your thoughts — no account required.

Didn't find your answer?

Ask the community — no account required