Direct digital synthesis of square waves (2023 Update)

It strikes me that John Larkin's original idea of synthesising trapezoids can be made to work.

You would still use a fast 14- or 16 bit DAC, but the waveform you fed into your comparator would be made up of four sequential components - all coming out of the DAC - high segment of arbitrary length, a falling edge, a low segment, and a risng edge

With a 14-bit DAC - the LTC2000 comes to mind

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you'd synthisese the rising and falling edges of the trapezia as 16-successive steps of a staircase waveform.

The LTC2000 can be clocked at 2.5GHz, so the rising and falling edges could be just 6.4nsec wide, and your maximum full amplitude output frequency would be a 78MHz triangular wave.

The trick is that you could have 1024 different rising or falling edges, with all the steps moved up or down in in steps of 0.1% of the full scale swing.

Only the first and last steps of the staircase would look different.

If you low pass filtered the waveform the zero crossing point would move across the 0.4nsec clock period in steps of 0.4psec.

The trick would be to use a Bessel - linear phase - filter which has a little bit of output ripple (figure 2.58 in Williams and Taylor) where the impulse response crosses the zero line, and put that point at the 3.2 nsec zero-crossing point ( picking the filter time constant to be about 0.64nsec, depending on the filter order) which would stop the odd first step from having much effect on the zero crossing point.

You could get any frequency less than 78.125 MHz, and you could step the period up in increments of 0.4.psec. 78.123 MHz would be the next one down

Because your filter only deals with rising an falling edges, you don't need to change it when you are synthesising much slower square waves.

It should work. I'd hate to build it - the LTC2000 comes in a ball grid array package.

Reply to
Anthony William Sloman
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søndag den 14. august 2022 kl. 08.51.36 UTC+2 skrev snipped-for-privacy@ieee.org:

since it is for a trigger and the falling edge probably doesn't matter, why not a single variable voltage step into a filter, sorta like a time-to-amplitude in reverse

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Reply to
Lasse Langwadt Christensen

My question is basically whether one can DDS a non-sinusoidal waveform to make a faster edge into a filter and comparator, to get better time resolution, less jitter, at low frequencies.

Conventional thinking treats the DDS as the tail end of a Shannon sampling system. But that requires that the signal that we're trying to make is perfectly bandlimited, which a sine is but a trapezoid isn't. So wave goodby to Shannon.

So we need to synthesize a fast edge, much faster than a sine, and poke that into an interpolation filter with a short attention span, one that sees the smooth part of the slope but forgets the sharp transition. Maybe synthesise an s-shaped rising edge to reduce the signal bandwidth some.

And of course we need to reach farther right into the phase accumulator bits, in real life or maybe by interpolation.

Hmmm, I could put a function, tanh or something, after the sine lookup in my DDS sim, to speed up the mid slope. That at least helps the comparator. Gotta think about that.

Reply to
jlarkin

Am 14.08.22 um 16:14 schrieb snipped-for-privacy@highlandsniptechnology.com:

You can take my VHDL design and have one of your FPGA guys replace sin(x) by sin(x) * tanh(x) and simulate it in a few seconds in Modelsim, Questasim or whatever you have. You get a pseudo-analog output.

The code that fills the ROM is a single process that feels like Pascal, no concurrency. The intermediate results are even files that could be used in Matlab.

That all does not have much to do with VHDL; I just choose VHDL because you need it anyway for compiling the chip. It could just as good have been C or Pascal; that would require more infrastructure such as gcc or turbo-pascal. It only generates a text file that is put into the ROM when builing the chip.

Cheers, Gerhard

Reply to
Gerhard Hoffmann

My DDS sim is in Spice. I posted that a few threads above.

I've parameterized it and added a sort of jitter computer; I'll post that soon. It's a platform for trying things out.

A 5 us run takes about an hour at 1 ps time step.

Reply to
jlarkin

I am only curious if I understand what you are after - is it some sort of "the larger the step the less low pass I want applied to it"?

Reply to
Dimiter_Popoff

That's a really clever idea

One could perhaps instead use a variable cap?

Reply to
Klaus Vestergaard Kragelund

When synthesizing a low frequency DDS sine wave, we step slowly through the waveform lookup table and a fixed filter doesn't interpolate waveform steps any more; it settles every step.

So, is there a better waveform to use at low frequencies?

Reply to
jlarkin

Hmmm. I get it now (though I don't get why this is a problem, likely specific to your application). I don't know how one waveform would be better for you that another, don't know what it is you are doing (perhaps you said and I missed it, I am not following closely). A pretty complex way of dealing with the steps at low frequencies is perhaps to have two DACs, one of them making the output filter programmable so you can dynamically change it, based on step, with some preemption etc., you get the idea - and I am not sure it is practical, not only because it is complex but also because I have never done this, I am just musing.

Reply to
Dimiter_Popoff

Your original idea was that a trapezium would would be better than a sine wave. If you keep the slope of the sloped bits constant, you can stick to the same the low pass filter time constant to smooth out the steps in the stair-case approximation to the sloped segments.

I just proposed a DAC based scheme for doing that.

Reply to
Anthony William Sloman

I missed the "we step slowly" in your post, now I get it. Well, the simplest way out is to step at a constant rate all the time. It will probably mean adding memory of course. Obviously you know all that and this is what you a re trying to wrestle, I don't think there is a better way to do it though (better than adding memory so your update rate remains constant).

Reply to
Dimiter_Popoff

I want to synthesize 1 mHz to 15 MHz, with a 100 MHz DDS clock. That needs a sine lookup table with about 50 billion entries. And an equally impossible DAC and comparator.

We'll probably wind up synthesizing the high range, an octave or so, and divide down as needed. The trick will be to make the gear shifts appear to be seamless.

That could get interesting.

Reply to
jlarkin

<snip>

Only if you chose to do that way. You could rewrite the look-up table every time you changed the frequency.

So think it out again.

What's difficult about that? It isn't as if there are any moving parts involved. The customer needs to tell you the frequency they want the machine to push out, and you need to be able to reconfigure it so that is the frequency which comes out.

Only if if you make life difficult for yourself by failing to tear up your original idea when it started looking half-baked.

Reply to
Anthony William Sloman

but what happens when you change from one frequency to another?

Reply to
Lasse Langwadt Christensen

Uh, the output frequency changes?

Reply to
Ricky

There are dilemmas. What exactly do you do when the frequency was 1 mHz, and you are 500 seconds from a trigger, and the user sets the rate to 10 Hz?

How about the reverse?

What do you do if the requested transition was from 1 Hz to 0.99 Hz?

Reply to
jlarkin

I would always stop the pulse generation during the settings change. The changeover can happen in one clock cycle of your master clock, so the circuit will resume with very little delay. The filter will be the slow part of the whole thing. The worst case delay from frequency change will be one new period.

Are you adding new requirements, that the delay between previous clock output and next clock output must always be within the range of the two settings? If so, then the actual change should be triggered off the output clock. It would result in a delay until the change of up to one old clock period.

Have you asked your customer how they would like for these cases to be handled?

Reply to
Ricky

Actually, this is an easy one to solve. I was picturing a fixed counter and selecting taps. But instead, use a programmable counter which is reset to zero and counts up to a threshold. If you change the threshold to a larger value, the counter continues counting up until the new threshold. If you change the threshold to a lower value, the counter will either continue counting up to the new threshold, or if it has already been passed, immediately reset and generate a clock edge.

This combination of a DDS and a programmable divider can give very good results as shown in many applications.

Reply to
Ricky

I still don't understand what you are trying to do. Periodic sine wave 1 to 15 MHz at 100 Msps is trivial, it takes a 100 entry sine wave lookup table for the slowest case. If you want to switch by operator action you have milliseconds of time to recalculate the table. If you want to switch by some external gating you only need two tables to switch between, this makes up to 200 entries. This is all way too simple and obvious so you must be after something more than that - which I haven't got yet.

Reply to
Dimiter_Popoff

only if you want neat frequencies that add up to 100M

Reply to
Lasse Langwadt Christensen

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