interleaved addressing in SDRAMs

Interleaved addressing was implemented to support cache line fills starting at a non-aligned address. For example if your cache line takes 4 words and your processor askes for word 2, the cache would start filling with word 2, then 3, then complete the line by filling words 0 and then 1. This reduces latency. Typical use of this mode is with Intel microprocessors.

For most FPGA applications, I would generally stay away from interleaved addressing. In addition to complicating your design, it restricts the maximum burst size of an access.

HTH, Gabor

Hi Gabor,

Thank you very much for the response.

This can be done with sequential addressing also. If the burst size is 4 and starting address is 1 In sequential addressing mode, memory gives back 1,2,3,0 In Interleaved addressimg mode, memory gives back 1,0,3,2

In both the modes, the word required for processor is given first. But, the ordering of the rest of the words are different. Can you please clarify.

-Sai