Hello I need information about Discret cosinus transform algorithms implemented in FPGA structures.
Any links, doc`s?
Best Regards
DCT in FPGA
Mar 06, 2005
4 Replies
implemented in
Did you check out
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Quick look I found:
Video Compress:
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JPEG Hardware Compressor
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Derek
Also check out Xilinx app notes.
The DCT from opencores.org are not that ideal for FPGAs because they uses too much resources (64 multipliers) but they are extremly fast (one DCT per clock). The one described in Xilinx XAPP611 is great if you have build in multipliers. I have implemented a bit serail approach based on distributed arithmetics as described in
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. It is quite slow (about 500 clocks per IDCT) but utilises mainly LUTs. With a little bit faster FPGA device you can achive the count of IDCTs per second you need for PAL resolution (720 x 576 x 25).
Regards Thomas
Thanks, but i need source code (my mistake) of DCT/IDCT algorithm in VHDL language. This is for my engineer project in High School (sorry for my english:)
Regards
U¿ytkownik "Thomas Gebauer" napisa³ w wiadomo¶ci news:d0hb9c$cri$ snipped-for-privacy@news.mch.sbs.de...
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rt01.pdf .
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