Hello!!!
I am using DCM component (which is a ISE6.1 coregen synthesizable module) in top level entity. This top level entity is to be ASIC prototyped using Certify tool. During certify flow, compilation and estimation of the flow is running smooth with out any errors. During partitioning process, i assigned the DCM component and unassigned nets ( which are in 'system unassigned bin' of Partition tree view) to the user FPGA U1. Then no unassigned components/instances are visible in 'system unassigned bin' of partition tree view. Then during synthesis process, the following error occurs.
Running board compiler... Board compiler completed
Board compiler: 0 errors, 0 warnings, 0 notes
Running job planner ..... Job: "Planner" terminated with error status: 3 See log file "~/rev_1/tst.srr" All instances must be assigned before mapping. Pleas view log file for a list of unassigned instances .
The .log file does not provide any unsigned instances. But it has following messages.
Synplicity Planeer, version 6.2/3.2, Build 089R, built Jun 5 2003 nwrver.c:564 Error: vpn: Unknown format character 'ü' Process took 0.523857 secs real time, 0.42 seconds cputime
Can any body suggest what was the error.
For your information, with out DCM component the entire certify synthesis flow is perfect i.e. Compilation, estimation, partitioning and synthesis.
Is the DCM output signals CLK0, CLKDV are depend on the derived clocks from the synthesis process? If not, what is the bug?
Looking for your valuable suggestions
sateesh