I've been tinkering with these nifty Microchip mcp6022 op-amps. I've run into some things that I don't understand (again). I'm trying to garner additional gain by using both halves of the dual op-amp. I have attached a sample schematic of what I was trying. You can see that the + input of U1 is biased at 1/2 Vcc (Vcc=5V), therefore the output of U1 idles at ~2.5V. That's all well and good, but when I tried feeding that into the + input of U2 (trying to avoid plugging in 2 more resistors), I find that the output of U2 stays locked to 5V (unless I ground the + input in which case it promptly causes the output to go to ground). I ended up having to change U2 to be setup like U1 with a voltage divider on the + input and feeding the signal thru a decoupling cap into the - input (thru R4 which had been disconnected from ground).
Now, what I was thinking is that U2 was trying to amplify the 2.5V input by
10 (or is 11?) which caused the output to remain stuck on the positive rail.1) Does that sound right? If that's the case, why doesn't U1 do the same thing with the bias voltage that is applied to it's + input? It has something to do with R4 being grounded?
After I modified the circuit to have the second stage (U2) work like U1, all was fine. So I then tried to balance the over all gain between the two stages. When I lowered the gain of the first section to 50, and raised the second one to 50 by using 2K resistors for R4 and R5 I also noticed that the noise level went up quite a bit. I thought that balancing the gain was the correct thing to do to minimize noise.
2) Am I just seeing the effects of the myriad of other impacts that I made by lowering the gain of the first stage? The noise is a 100kHz signal coming from another circuit that is apparently being picked up by microphone leads. Perhaps by lowering the gain of the first stage, I tilted the frequency response more towards level causing the highs to be rolled off less?The desired signal is in the 500Hz to 1kHz range (clock ticks).