4013 question

"eatmorepies" schreef in bericht news: snipped-for-privacy@mid.individual.net...

What did you connect to the D input? It should be connected to not Q to get the required memory function.

petrus bitbyter

Do you have a clean, fast (enough), debounced clock signal?

Is the power supply to the chip bypassed?

It sounds like you're double-clocking the chip, for one reason or another. Why it happens to prefer one state over another -- I dunno. But cleanly capturing events like this can be a bitch and a half.

How about the clock edge-rate? ...Jim Thompson

Sorry - forgot to mention I had connected pin7 to 0V.

I've just tried again with the inputs of the second Dtype grounded - R, S, Clk and D. No change in the circuit's behaviour.

John

I don't know because I don't have a scope. I'm guessing the pulse flash on the logic probe tells me the clock signal isn't clean.

I'm not sure what this means. I have a 0.1 microF ceramic decoupling capactior across the power supply.

I think you're right.

Would a Schmitt nand (4093) configured an an inverter be sufficient to de-bounce the signal? if not what do you suggest?

John

I've just tried the 4093 Schmitt NAND (I put 2 inseries to make a Schmitt AND), The circuit is much improved and it switches states cleanly about 8 of

Now. How to make the initial pulse last longer using some kind of monostable with a delay before it falls back to it's stable state?

John

It sounds like you've found the answer with your 555 circuit, but if you Google "debounce circuit" you'll find a bunch of suggestions.

Note that debouncing is as much an art as a science, so expect that you may have to make a couple of passes to get it right.

an easy way to do that with what you have is to put a R-C low-pass filter between the two schmitt NAND stages.

______ ______ .--| __ \ .--| __ \ ---+ | _// )O---[100K]---+------+ | _// )o--- `--|______/ | `--|______/ === | 100nF 0V--+--

--- _ Probably not much of a concern since he's seeing action on Q and Q. _ Since Q and Q always wind up in the same place after the clock is asserted, I'd suspect double-pulsing on the clock input.

Relatively slowly, too, since his double Schmitt trigger only cured the problem 80% of the time and that handy-dandy 555 with a 2 second delay did the trick. ;)