Hi, In my design i have two counters, a write_counter and a read_counter, both are 11 bits wide. I used a simple compare equation like this:
assign last_byte = odd_number_bytes ? (read_counter + 2 == write_counter) :(read_counter + 1 == write_counter);
and last_byte triggers the state machine etc etc. now the logic designed by this comparator is of 6 logic levels which is causing a timing failure in my design. I need to optimize this logic but i can't seem to think of any fast implementation. I tried to come up with something like a lookup on first two LSBs and XOR the other bits etc, but every solution that i come up with contains a lot of corner cases and the whole thing starts to get messy. So, can anyone help me with this logic's optimization? Perhaps a fast implementation or a way to optimize it. Thanks a lot.
Regards
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