Compact Flash Peripheral Design with FPGA


I am currently involved in designing a Compact Flash Peripheral --- a GPS Receiver for TDS Recon or PocketPC. The power consumption is very critical. Does anybody know any xilinx parts have requirements close to or less than 100mA?

Could anybody please let me know the advantages to use FPGA for the CF peripheral, other than a DSP or ASIC? You know the price is quite different.

Is it important for the CF GPS Receiver to support all three modes of CF (Memory, I/O, and True IDE)? If we want to support all 3 modes, which one is a better choice for the project, FPGA or DSP?

Could anybody please

Thank you very much in advance.


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Hi Johson,

For your work, FPGA and CPLD devices are not the good choice : very expensive and very bad for critical consumption applications.

You have to work with a low power cpu like a simple PIC or an AVR (8 to

16 bits).

We have done an datalogger application using a CF and a PIC cpu. This application emulate Memory read/write access from/to the CF via the IO ports of the PIC. Also, we have a file system in the PIC cpu able to read and to write and manage different files in the CF.

Also, you will be able to emulate TRUE IDE from the PIC IO port if it is needed.

The choice of the cpu will be depending about the rest of the design.

Actually, we are starting a new datalogger using a Philips ARM 7 PLC2106 (32 bit cpu) + CF + many AD/DA. In this new project, a 32 bit cpu is important because we need to process many external inputs/outputs. (also, we are thinking to use an CPLD for accelerating some processing JOB)

For a GPS receiver application, a 8bit or 16 bit cpu will be enough -> low cost and low power.

NOTE: we done last year an application with GPS Receiver. Also, we may design your application very quickly merging our know-how from our two precednet projects : CF file system + GPS receiver.

Best regards, Laurent Gauch

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Amontec, Larry

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