Sleep mode of Compact Flash Peripheral


I am about to develop a compact flash gps receiver for PDA (TDS Recon or PocketPC or others), and the power consumption is very critical.

A senior CF developer suggested me to use low power microcontroller such as a simple PIC or an AVR (8 to 16 bits) for this type of application, other than FPGA/CPLD, because he thought FPGA is very expensive and very bad for critical consumption applications.

I think he is right if I only want to do a simple interface between the GPS OEM and the PDA. However, I am thinking about to provide more functionalities and flexibilities, like to support "Sleep" mode of the GPS OEM to save power further and the customer can modify the sleep time from an utility software at PDA side. Moreover, I want to support all three modes of CF (Memory, I/O, and true IDE), (not sure how important they are). Could anybody please let me know which design is better for these functionalities, low-cost FPGA/CPLD, or low-cost DSP, or low power microcontroller?

Thanks in advance.


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