Your design would be much simpler if you had an input clock that varies between 1.3 and 1.6 MHz. You could then easily generate the 32-times lower clock frequency with a 5-bit counter. In your case, you have to build a feedback (or servo) system, that multiplies the frequency in an indirect way: it adjusts a variable high frequency (1.2...1.6 MHz Voltage-Controlled Oscillator). This high frequency is divided by 32 in a 5-bit binary counter, and the output of this counter is compared (in a phase/frequency detector) against your incoming 39 to 50 kHz clock. Any frequency or phase difference generates a control signal that, appopriately filtered, changes the VCO frequency in the right direction. A long time constant in the Low-pass filter gives you a very stable frequency, but slows down the response to any frequency changes of your incoming clock. A higher cut-off frequency in the Low-pass fiter gives you less stability, but better agility. There are many textbooks that describe PLL (Phase-Locked Loop) design. Any FPGA can implement the counter and also the phase/frequency detector, but not the VCO. Peter Alfke, Xilinx Applications