Asynchronous memory in Stratix devices

What if i design an asynchronous memory in Stratix devices?? Will it create any design problems??

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Hi vlsi_learner,

If you model fully asynchronous memory in whatever modern FPGA it will be implemented as latches (= 1 logic cell) behind a big address multiplexer. If it's 32 bits in total that's not a big problem but if you go for several Kbytes then, yes you're in trouble.

Best regards,


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Ben Twijnstra

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