Asking about FPGA-SPARTAN error in synthizer

H.Azmi wrote: : what can cause this error : : ERROR: a gnd net is driven by primitive gate(s) -- NET: GND0

You overwhelm us with information.

Do you do schematic capture for your design? I guess you connected some gate output to ground.

Bye

I have seen similar things generated by synthesisers When this has been the problem the net is driven by the output of a lut. The lut has a constant value output and has no inputs. To find if this is the problem use FPGA EDITOR to look at the design, select the net from the list window and use the attrib button to bring up the pop-up window. Then select the pins tab and you will see the output and inputs of the net.

If this is your problem check to see if you are synthesising for the correct part. This sort of structure is sometimes valid in families without built-in pull elements. Otherwise try and change your logic, or synth options, to get a different synthesis that might not have the problem.

John Adair Enterpoint Ltd.

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