Altera's NIOS2 examples...

Looking at the NIOS2 1.1 design examples I wonder why in the "standard" design the SDRAM pll is of type "Stratix" though the design is for the Cyclone board...

And did anyone manage to clock it at more than those lousy 50MHz?


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You can reach 100 MHz without any problems. I will recommend to use "Timing Optimization Advisor" for hints how to improve fmax. After synthesis with clock constraints, I get ~102 MHz in Cyclone (C7 speed grade).


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Hi Nick,

Cyclone uses a PLL that is functionally equivalent to one of the PLL types from Stratix. Us software engineers are kind of lazy -- we reuse code where we can, and in this case it means that there is a rather unintuitive "stratix" flag for the PLL!

Make sure you've applied a timing constraint to the clock in question.

- Paul

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Paul Leventis (at home)

I clocked a NiosI on my Cyclone board at 140MHz running from onchip sram and

112MHz running from sdram. Haven't rerun the test with NiosII.

But MHz isn't that important here. The problem is that it takes a minimum of 5 clocks to access onchip sram and 11-12 clocks to access sdram.


Reply to
Kenneth Land

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