Caching of external memory

Hi.

We are working on a Virtex4 FX12 PowerPC system. The code below is stored in BRAM and so are the stack and heap.

Using cache on the external memory crashes the program after approx.

10000 checks. When only caching BRAM it works fine.

The program below clears the memory, then it checks half the memoryspace for zeros and writes the addresses of the zeros in the other half.

Any sugestions why caching of external memory doesn't work?

/////// CODE ////////////////////

#define CHECK_BASE_ADDR XPAR_DDR_SDRAM_32MX16_MEM0_BASEADDR #define CHECK_HIGH_ADDR (WRITE_BASE_ADDR-1) #define WRITE_BASE_ADDR (XPAR_DDR_SDRAM_32MX16_MEM0_BASEADDR+0x02000000) #define WRITE_HIGH_ADDR XPAR_DDR_SDRAM_32MX16_MEM0_HIGHADDR

Xuint32* CheckPtr = (Xuint32*)CHECK_BASE_ADDR; Xuint32* WritePtr = (Xuint32*)WRITE_BASE_ADDR;

int main (void) {

ClearMemory();//write zeros at all memory locations

XCache_EnableICache(0x00000001); XCache_EnableDCache(0x80000001);

while(1) { if(*CheckPtr==0) { *WritePtr = CheckPtr; if(++WritePtr > WRITE_HIGH_ADDR) WritePtr = WRITE_BASE_ADDR; } if(++CheckPtr > CHECK_HIGH_ADDR) CheckPtr = CHECK_BASE_ADDR; } }

Reply to
Rune Dahl Jorgensen
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Hi.

Just an update for anybody reading this thread later.

We found a work around. After updating from EDK 8.2 SP1 to SP2, we where able to connect to the memory through the PLB instead of the OPB bus. This change made the cache function correctly.

It was a beautiful and sunny day when Rune Dahl Jorgensen wrote news:Xns988CA6BF53518runedahl23223@130.226.1.34 in comp.arch.fpga:

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Rune D. Jorgensen
Reply to
Rune D. Jørgensen

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