adding FPGA grounds

I have seen some manufactures suggest this. I haven't measured it, but I would guess it could help, at least as long as the FPGA doesn't every try to drive the output high for a moment.

What problem are you trying to solve? My experience is when it comes to po wer distribution systems (PDS) people often try to optimize without knowing if they have a problem. PDS design is one of those things where you can e ither try actually analyzing the design to know how to design the PDS, or y ou can throw in a lot of overkill to try to make sure you hit the rabbit.

What will you measure to see the effectiveness of the grounds? The usual c oncern is ground bounce. For that you would measure an output pulled low w ith no trace to see (as well as possible) the internal ground voltage. I'm not sure how well the internal spike will be conducted through the pin dri vers. Otherwise you would need to load a design into the chip that would p roduce similar switching spikes as your real design and see if you get any false triggers on clocks or input corruptions. I suppose a simple input di rectly driving an output can show a corrupted input level differently than an output at a fixed low level showing the ground bounce directly.

For the final design the outputs would be hardwired to ground eliminating the possibility of driving to any other state.

If they were 'hard wired' they wouldn't be programmable! The issue is that if in the configuration process, it was possible for a momentary glitch to turn on the high driver, you would get a current spike. They do try to avoid this, but sometimes, particularly during the power on transient, strange things can happen. Some parts definitely will turn on weak pull ups which will draw power till they get the pull ups configured off.

If some Nvidia ^H^H^H^H^H Xilinx documents proposes, consider it. Otherwise not!

There are protections in the chip to prevent loading a corrupt bitstream. This isn't just a simple SPI register load.

No pull up to the power rail burning up an I/O.

How do you know these pins are not some sort of manufacturing test output pins?

On a networking chip I used (years ago), a couple of the pins that were documented as power and ground pins were actually mode configuration pins.

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He is talking about wiring unused I/O pins that he can specify as grounds o r power by assigning a '0' or '1' respectively. They are not the same as a solid connection to the chip ground or power, but every bit helps. At hig h frequency the pin inductance is probably higher impedance than the resist ance of the internal MOSFET, so the I/O grounds are probably a lot better t han nothing. But this is also needed on the I/O power supply as well as gr ound.

Maybe newer FPGAs have less problems with it, but I seem to remember that some FPGAs comming out of configuration (and defaulting to be an input) into an output, always enabled, driving low, might not complete keep the high side driver off. These FPGAs specifically defined that unused pins should be left floating/not connected.

IF the chip designer is presuming that small glitches on enabled output are unimportant (since they will only be driving inputs), this isn't unreasonable.

Later, with higher density packages, the idea that grounding low driving outputs could improve (slightly) the ground impedance, made it more important to avoid these issues.

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ting the possibility of driving to any other state.

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m. This isn't just a simple SPI register load.

Can't say I follow what you are saying. It's not like the I/Os are not con figured while the rest of the chip is configured. If unused the I/Os are c onfigured as inputs, either with a light pullup or nothing, I don't claim t o know the details, but an I/O should never be left floating since that all ows the input (which is always connected) to drift to a mid voltage where b oth high and low FETs are on drawing high current.

When unused, the software takes care of the default I/O configuration. You r reference to the high driver being partly on is probably the pullup which is implemented as a very light FET.

If you configure an output as driving a constant '0' (no longer an "unused" I/O) it will be driving the output hard to ground. There are various driv e strengths and the highest should be used. Connecting the pin to the righ t power rail will provide some reduction in ground impedance just as a simi lar act on the high power rail will do the same for the high side.

Sorry, I'm not following. Ground bounce is about outputs switching large c urrents at the same time driving the ground impedance and driving the chip internal ground high which impacts the threshold voltage for *inputs* causi ng glitches. I'm not clear what you are saying about outputs.

Sorry, I'm not following what you are saying at all. What is the issue tha t needs to be avoided???

If you don't understand HOW a FPGA works internally, then you don't really have a basis to comment.

At reset, before the configuration is loaded, the pins will be setup as inputs, and the designs are careful to make the Power on Reset to Default Input configuration glitch-less, as it is expected that some of these pins will be driven by low impedance drivers.

There are also Flash/OTP parts that don't have a 'configuration' phase, but at power on 'immediately' configure and might enable before the output value is fully set.

My comment was that some designs didn't switch from Default Input mode to Enable Low Output in a glitch-less manner, in part because it wasn't expected to be important. An output was expected to be driving a relatively high impedance load, so a short power on glitch was not important.

Some chips DID specifically define that unused pins should be left floating. (The compiler tool converted them to weak outputs of seemingly random signals). Some actually will disable the input section, so the mid-level voltage isn't a problem (especially useful if the pin can be multiplexed with analog functions, where mid-level voltages are expected).

Outputs have (at least) two FETs, one to pull high, one to pull low. Just because you have programmed the FPGA to drive low, doesn't mean that the high driving FET has gone away. Depending on design requirements, they might be careful to avoid the glitch or they might not. It costs logic to sequence things to happen in a given order, so if it isn't important, they might not add the logic to prevent the glitch.

I am talking about an initial power on glitch at the transition from Power-om/configuration to operation. Grounding an output that has a high driving glitch can create a significant current spike which can disrupt power supplies and chip operation.

If a chip does not have a guaranteed glitch-less startup configuration, don't assume it does and tie and output to the 'presumed' output level (that you have configured).

configured while the rest of the chip is configured. If unused the I/Os a re configured as inputs, either with a light pullup or nothing, I don't cla im to know the details, but an I/O should never be left floating since that allows the input (which is always connected) to drift to a mid voltage whe re both high and low FETs are on drawing high current.

Your reference to the high driver being partly on is probably the pullup w hich is implemented as a very light FET.

sed" I/O) it will be driving the output hard to ground. There are various drive strengths and the highest should be used. Connecting the pin to the right power rail will provide some reduction in ground impedance just as a similar act on the high power rail will do the same for the high side.

Dude, if you can't discuss a topic civilly, then don't discuss it at all. Either maintain low cones or don't reply.

You have done a great job of explaining the configuration of the I/Os but n ot connected that to the issue at hand which is the use of I/Os as ground c onnections. You talk about an output driving low and then say the "high dr iving FET has gone away" without explaining the significance. No, transist ors on a chip do not "go away". So what?

ge currents at the same time driving the ground impedance and driving the c hip internal ground high which impacts the threshold voltage for *inputs* c ausing glitches. I'm not clear what you are saying about outputs.

You have not explained where this glitch might come from.

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that needs to be avoided???

Nothing in digital chips are guaranteed glitchless. That's why we provide so much decoupling of the power supply, to damp the glitches. You have not explained yourself at all, but seem t o be simply claiming tying a low out put to ground will produce a large glitch on configuration. However, you d on't really explain this glitch, you simply state the "high driving FET ha s [not] gone away" whatever that means. Why would the high driving FET be turned on at any point in the configuration when the configuration is to dr ive low?

Perhaps you can review your explanation and find the gap in your logic, bec ause you have failed to explain your logic?

Nice links, thanks.

I have a time-critical async signal ripping through this FPGA, and there is also a 40 MHz clock and some SPI activity. Ground bounce will add jitter to the critical signal. The ground pins are clustered towards the center balls, so maybe we can create a bunch of fake, low-Q grounds around the edges of the chip, with better connections to the ground plane. We could even play with drive strength.

We'll try it and see what happens.

YOU, who admitted that they don't fully understand the details of how things work in a FPGA was telling me, who has worked with them from their beginning, that a phenomenon that I HAVE seen, "Can't Happen". Who is talking through their hat?

Because it is there, it CAN turn on, at least momentarily, causing a short from the power rail to your external ground connection, which wasn't supposed to be there by the manufactures design specs. (Pins declared as outputs need to be driving loads with a given minimum impedance, not a zero ohms to ground)

The output stage gets two inputs (of interest here) from the main FPGA array. One is an output enable, which for proper operation during power om reset/configuration needs to be internally biased during that period to 'disabled', and a second 'Data' bit, that since the value isn't needed during this initial phase, might just be left undefined. to define in at this time either needs a light restive load all the time, burning power all the time, or a transistor (space) or a more complicated coming out of config sequencing (again space).

At the moment configuration ends, the system copies the configuration data from the configuration shift register or flash memory source into the actual operation registers, at which point the enable will start to be driven, as well as the data. This action takes a finite period of time, and unless special care was taken, the output enable my reach the output before the output low signal does, at which point the output might glitch high causing the current spike. Since this also happens to be a high activity point in time, such a spike might disrupt the FPGA.

Later designs often did decide it was worth the cost to sequence things, so most FPGAs today delay the enabling of outputs a bit to allow the data paths to settle before outputs are allowed to drive.

Actually, many designs HAVE located places where glitches in the earlier simple designs caused enough problems that they have taken care to reduce or eliminate many of them. For example, most LUTS today are promised to not glitch if a single input transitions, and the LUT value for both cases are the same (some earlier designs this was not always true without special coding).

It may be possible to improve ground bounce slightly, but the on-chip ground connections may be connected only group-wise, so that the drivers for SDRAM buses etc do not force ground bounce on the GND of the low level core signals.

But driving unused outputs to GND cannot be bad since your logic might require it and there can be no bus fight.

Long time ago, I had a bus fight between an XC3020 and a 74AS244. The AS244 said low, the xc3020 said high. Saying low is the easier part, but the XC3020 won hands down. That consumed a lot of current. :-)

Early FPGAs could do that with their on-chip tri-state buses on their own, just by feeding them corrupt configuration data.

I had to study Virtex power up in quite detail when I implemented configuration memory scrubbing for some space-bound Virtexes that may encounter radiation and get bit flips in configuration ram.

Mitigation consists of re-loading the configuration ram from non-volatile memory every few minutes and doing the user land logic triple module redundant. Refresh must be done before the errors pile up so badly that the redundancy fails.

FPGA configuration is a well defined synchronous process controlled by the configuration clock. Scrubbing is done just like a power up, but the process is aborted 1 clock before the global reset etc is executed.

It is possible that the FPGA controls its own scrubbing. Having bugs in the TMR logic that controls that scrubbing is ugly.

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And the mother of the really dumb ones is always pregnant. I saw someone complain that his FPGA did not really work. He had used the FPGA ground pins as GND bridges for his board layout, forcing board currents through the chip! =8( )

Cheers, gerhard

I don't know why they would insist the added grounds needed to be near the existing grounds. I really can't see the advantage. I would expect the ad ded grounds should be as close as possible to the high speed I/Os that are causing the glitches.

By all means, don't make your drivers any faster than they need to be. Tha t is the one direct control you have over the problem.

The other factor is that you need the same treatment on the power rail for the output I/Os. There is also a matter of the high speed outputs being br oken up. If you spread them in time you will see less impact on the input threshold. So if you have a small number of inputs you wish to protect, yo u can put them on one output bank, then put the high speed outputs on the o ther banks with the added grounds and I/O Vdd connections.

I suppose with the die being smaller than the package, it makes sense to ke ep the added grounds close to the center of the package so their series imp edance is minimized. But reducing the ground bounce by staggering multiple outputs switching at once will help a lot more.

If you don't have multiple signals switching at once, I suppose you are ch asing very small effects and will need to apply every technique you can com e up with.

put pins?

pins.

ds or power by assigning a '0' or '1' respectively. They are not the same as a solid connection to the chip ground or power, but every bit helps. At high frequency the pin inductance is probably higher impedance than the re sistance of the internal MOSFET, so the I/O grounds are probably a lot bett er than nothing. But this is also needed on the I/O power supply as well a s ground.

Sorry, not sure what you mean by "group wise". Grounds are connected to gr ound, typically a ground plane. What is "group wise"?

Why do you emphasize the ground an ignore the power? The problem comes fro m the threshold of an input being impacted. The threshold is based on the differential voltage of the power and ground. So is it not correct that th e power rail will also impact the input threshold?

I'm not clear why you are mentioning "bus fights".

My understanding is that all FPGAs have protections against accepting inval id configurations. I may be mistaken. It's just that I am pretty sure thi s was resolved so long ago that I no longer even give it a thought.

Yes, that is a different matter. I worked with a guy from NASA for a while who was radiation testing FPGAs and he explained how they would reload the configuration periodically to deal with soft errors. What he never explai ned was how the circuit functioned while the FPGA was being reloaded.

So how do you deal with the loss of the FPGA functionality while being reco nfigured?

So is the FPGA never stopped? The devices I've worked with start configura tion by resetting the entire configuration RAM. It was explained to me tha t was what was happening that set the minimum configuration time, one full cycle through the process. As long as the configuration pin was held asser ted, the process would continue. When you released the signal it would com plete the cycle it was on, then accept a new bit stream. I think Xilinx us ed the INIT pin for the flag that it was ready to be configured which could be paralleled between multiple devices.

I recall learning not to connect ground traces that way when I was working with 8 bit micros... from someone else's experience, not my own. I was tol d about it.

groups might be a GTX transceiver , a tile of CLBs, a hard SDRAM interface.. WE cannot know that, but it could make sense. We can just bet or try it.

Because JL wants to add GND connections. It's in the title of the thread.

And input thresholds do not depend on VDD in the first or second order. That is determined by active circuitry in the chip and is set by configuration data. Remember you can choose 3V3-LVCMOS or 2V5 or 1.8V logic, or whatever.

And for powerup, VDD rise time and monotonous rise is usually specified.

Mentioning XC3020 should give a hint about the time frame. We had stacks of Compaq-286s then for concurrent runs of apr, in the hope that there was a usable routing solution the next morning.

The Virtex is never stopped. The user-land circuit continues to run while the configuration ram contents is rejuvenated in dual port style. That takes a known number of CCLKs from the activation of the program command pin. A few CCLKs later, chip re-initialization would start: global reset etc. That must not happen, so the configuration clock must be stopped in time until after the next program command a few minutes later.

Scrubbing does not make the FPGA radiation proof. Important logic must be triple module redundant.

Since I was not given the Xilinx TMR tool (ITAR..) I wrote a VHDL library with tmr_slv, tmr_signed etc that looks much like the normal standard_logic_vector etc and hides most of the redundancy. I prefer my own library now. :-)

Yes, scrubbing can have unexpected side effects. For example, you may not use these 2*8 bit CLB RAMs because they are physically in the configuration RAM.

Unfortunately, the Picoblaze uses these for its registers. Our software people did not like it that their programs crashed every few minutes.

I have rewritten the Picoblaze to use ordinary flipflops for its registers. The performance and area drawback was acceptable.

Cheers, Gerhard