What are the rules for coding a bidirectional databus in VHDL?
I must be able to connect several different entities to the same bus, and all entities but one has its outputs as 'Z'.
Should the bus signals be declared as inout?
That's the rule.
I would prefer to use separate data_in and data_out buses. There are no real tri-state nodes inside the fpga.
-- Mike Treseler
That's good advice from Mike. The tools will translate your 'Z's and stuff into muxes anyway, so by having the seperate busses, things will be clearer. HTH, Syms.
Isn't that going to make it more difficult to maintain if new entities are added in the future?
I don't think it need be more difficult, just different! If you plan it right from the start, I think you'll be just fine. You also won't be tearing your hair out trying to find signals in Chipscope that've been turned from tristates into muxes. But, YMMV, either way will work. HTH, Syms.
Even though there are two buses instead of one, I don't have to think so hard about wiring them up. And not all additions are structural. I can add internal registers and ports to my design without adding an entity.
-- Mike Treseler
If you do not have multiple devices on the bus writing data to multiple other devices (usually if there is only one master), then using two buses (read & write buses) eliminates the false timing paths that can occur with a single bus (originating from one slave and arriving at another), and is just as easy to wire up. Otherwise, having two buses is harder.
Andy
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