The only FF devices I can find with a high true reset control are the CD401
3 and CD4027 and the part number variations of those parts. Is this it? D o none of the AC, AHC, HC, VLC,... use high true resets?I thought there were parts made in the HC or AHC technology with the 40xx n umbers and functions, but I'm not finding them at digikey.
The circuit I'm using it in is a hybrid analog/digital thing. I want to de tect a voltage (representing a motor current) has risen above a threshold f or some amount of time, then set a FF that controls power to a motor, disab ling the motor.
I went through an iteration of this circuit using MOSFETs (1 N-channel and
1 higher power P-channel) to form the FF and two more to provide control fr om lower voltage inputs. The input that turns the motor off is from a comp arator that detects transitions above the threshold. The output is OC with a pullup and a cap to act as a timer. Reaching the threshold of the input control FET flips the flop turning off the motor. The other input is from the MCU to turn it back on. Another FETs is used to detect the state of t he FF to match the MCU input voltage.Using a proper FF allows three of the transistors to be removed and a few p assives. The level of the RC output from the comparator is used to control the reset input to the FF. The MCU input is direct to the clock input whi ch with the D held high sets the FF. The FF output then drives the FETs th at control the motor. Simple. But...
I'm concerned that this is using the input threshold to set the level of th e RC on the output of the comparator. It looks like it can cause a range o f 50 to 200 ms to detect the high current condition. I was hoping to find a different flavor of device with a better specified input spec, but this r equires a high true rest and there only seems to be two PNs that have this, CD4013 and CD4027.
I'm pretty sure the variation in timing is not at all important. This is t o detect the motor running to the stops if the software craps out. Turning off in 50 ms won't be so different from 200 ms I expect. It's not like we have any hard spec. This project is running pretty open loop in that rega rd.