Zero operand CPUs

Zero operand just means that the top of the stack is the implied operand for most instructions. It means that a register decoding phase is not needed in the execution of instructions because the operand is the stack.

Instead of having to decode which registers are gated for input and which register is gated for output, and set up the gates to the ALU as some of the steps in executing an instruction the path to operands is hard wired because it is the top of the stack. So there are no operands to decode.

It is not very clever to try to convince people that it means that there are no arguements at all and thefore all it can do is NOP.

It certainly does not mean that it cannot do useful things. After all some languages like Forth are also zero operand because they use the top of a parameter stack. Parameters are still needed for branching and for literals but they are not operand fields for registers that require a decoding phase hence the name zero operand.

Some people will declare that programming a register machine is just easiter than programming a stack machine. Their argument is that the compiler they use makes it easy or that they can stay at a higher level of abstraction.

Some people will declare that programming a stack machine is just easier than programming a register machine. Their argument is that their compiler and language is simpler and smaller and doesn't need all that complicated register stuff. They may say that to program a register machine people need complex smart compilers to hide the real complexity under the hood and they prefer something simpler.

And all that is mostly a matter of whether they are thinking of software in a style used on register machines or a style used on stack machines or virtual stack machines. If you use C then you like C hardware and C software and may think stack languages or stack hardware is harder for you to deal with.

If you use Forth then you may think stack software and stack hardware is a lot simpler and easier to deal with than bigger more complex tools and platforms. People choose Forth for embedded work to get smaller, cheaper, and lower power solutions to problems than those available with the bigger more expensive, more complex hardware and software.

Which is easier depends entirely on what you know and the problem at hand.

Yes of course. The idea of 'zero operand' is that the arguments, operands, are on the stacks. It's just silly and stupid to argue that it means that there are no arguments and thus nothing useful.

And it may be easy to port software far more compact and space efficient than register machine native code especially when the design needs inlining and loop unrolling to ger around pipeline or cache problems.

The idea is to also reduce power consumption and resources required by the design. The idea is to be able to execute more compact stack based code than register based code to further reduce cost and power consumption by reducing memory use. The idea is to make the CPU easier to program and more efficient with simple software rather than demanding the biggest and most complex development tools.

That's just insulting and dumb. Zero operand does not mean NOP only. ;-) That's a new Forth-hater sound-bite, Forth and stacks are only good for doing NOPs. Only the most ignorant will believe it. ;-)

It did not have to be told!

Best Wishes

Reply to
Jeff Fox
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too bad the S-6 is delaying sooooo looooong so others than the few EA companies can develop code for S-6/V-6

LUT6 hopefully means also SRL64 what would be cool, but eh it should be now a few months til the 11.1 release so the mortals will see the spec too then

Antti

Reply to
Antti.Lukats

OK, same then: a TOS can not be the only operand. You very probably mean of course that the stack contains the operands. This is indeed clever but does not mean "zero operands". Regarding this "register decoding phase" - well, you have to "decode" it if you make the distinction between "operation" and "operand". But if you see "ADD A,

1" as a different operation than "ADD B,1", you do not have any "phase" in front of knowing what operation is needed. It simply could be two different operations. So if you term a "stack" layout based thing "zero operand" you could also call every "register" based layout to be "zero operand", as far as every register has its own implementation of "ADD".

There are still operands to decode. It might be the stack is somewhere in memory or it's something like a few registers without possibility to address them. There are still operands and they need to be addressed and as that also "decoded" (even if this is not needed by the symbolical instruction representation called "machine code").

Well, without further instruction, everybody will think it is so.

;) OK, that declarations does not interest me, as far as even mobile phones start to be implemented using x86 technology...

OK, in Forth:

: foo dup ; : foo1 ! ; : foo2 swap foo tuck foo1 ;

This now looks like a completely "useless" complicated sequence, nobody would write this way. The truth is, that the more you use that nice "symbolic" stuff in Forth, the more that "useless" complicated sequences occur in output. If you want to allow your users to use that symbolic stuff - and you want to avoid too "useless" operations, even the stack based compiler- thing has to optimize. Except for few, simple loophole-optimizations, the stack based design of a processor does not help with it. The compiler gets at least as complicated as every other - or maybe even more complex (this would have to be done first I think).

OK.

Sure? I mean the "problem at hand"? It would be interesting to know if there are differences depending on the problem.

;)

Regards,

-Helmar

Reply to
Helmar

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Jeff & Helmar

another holy war?

there are pro and contra for everything.

what is sure is that as of today the register based (or maybe 0 register ones like mproz3) small FPGA oriented soft-core processors are EASIER to deal with then those that are forth like and stack based .

be the reason inbetween the ears, or in bad documentation or missing tools, whatever. Thing is non-stack based small soft-cores are easier for normal FPGA users .

I would not mind if it would be the other way around, but it isnt. So some forth guy could make some effort to describe and document the use of some small SoC that uses stack - based core and is not programmed in C (that is some thing else then ZPU what is stack cpu with GCC support)

Antti (hm i should look the B16.. again )

Reply to
Antti.Lukats

Studying first-year computer science (machine architecture) might be helpful to you, since this is very standard terminology. Of course relatively few people have worked on zero-operand ISAs but I guess most people in this NG have worked extensively with 1- and 2-operand machines, and probably 3-operand also.

Reply to
zwsdotcom

What instruction is a CALL? How do you specify the address? How do you specify literal data?

Rick

Reply to
rickman

Obvious is that I only studied it the first year (it was in conflict with my "philosophy"-schedules). And in this case it did not help, since I studied "formal logic" after it. You should be sure that I know that 2-operand machines would be acceptable for me, while I do have problems with 1-operand too (may it be zero "0" or not). I btw. can not even remember that some operations had no operands at all - except maybe something like NOP, while even this had "operands" like the program counter that would be increased.

That far, be nice not rude,

-Helmar

Reply to
Helmar

What are you talking about. I saw your other post and realized immediately that you were making a joke. I saw Jeff's reply and realized that he misunderstood you. Then I saw this reply and realized that I was wrong and you ***WEREN'T KIDDING***!!!

Man, some people just don't get it. Some of the stuff you say below is either from lala land or you are still pulling people's legs.

So are you for real? Is your real name, Amelia Bedelia?

Rick

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Reply to
rickman

You want an answer from *this* writing below? Are you kidding?

-Helmar

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Reply to
Helmar

$addr ,

Reply to
Jacko

Maybe it's you ;)

Regarding my real name: Helmar.

What you and others not get is: "Zero Operand Cpu" is something like "Wir sind Papst!" in Germany. Why did not FORTH INC., forth.com make advertise with "The Zero-Operand Language!" all the last years? It would save a lot of time for programmers, not to care about operands. I guess they do not for good reasons.

-Helmar (...censored...)

Reply to
Helmar

o

Jacko

your comments are just getting more and more fuzzy and cryptic.

is that on purpose?

Antti

Reply to
Antti.Lukats

do

$addr , is not in conflict with a CALL. For a literal Jacko has to answer for my understandings.

Regards,

-Helmar

Reply to
Helmar

sh

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Jacko:

....ummmmm....

does NEVER make sense in a document describing an IP core.

not in my world (sure maybe i live in the wrong one)

Antti

Reply to
Antti.Lukats

I suppose, most have worked with a 0-, 1-, 1 1/2-, 2-, 3- and 3*1/2 ADDRESS machines but none with a 0- or 1- OPERAND machine.

An add instruction always needs two operands and has one results. But if you use a predefined location (stack, accu) for some of them then you can omit the address information in the instruction.

Reply to
Herbert Kleebauer

Maybe 'implicit operand' would be a more accurate description.

Reply to
Dombo

Ooh yeah - been there, done that. Big believer in the idea that if it's designed right, all you have to worry about is typos.

Haven't used an ICE (or a debugger) in about 25 years.

Steve

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Reply to
Steve at fivetrees

That is almost the first sensible comment I've read in this thread.

Steve

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Reply to
Steve at fivetrees

o

How many bits are in an opcode, 4 or 5? I would say it has to be five or there is no way for the machine to distinguish between an opcode and an address. In other words, there *has* to be a CALL instruction, even if it is just a one bit opcode with the rest being the address.

Rick

Reply to
rickman

Everyone here who is objecting to the concept of a zero-operand CPU seems to be defining the term for themselves and then arguing about it. A zero-operand instruction set is not one where the operators

*have* no operands. It is one where the instruction has to *specify* no explicit operands. The operands are ***implied*** by the architecture of the machine. e.g. a stack machine can use the top two elements of the stack as the operands and can put the result back on the stack. No operands need to be *specified* because that is *implied* in the architecture.

Why would anyone want to argue about the name of a concept rather than to *ask* someone to explain the concept?

Rick

Reply to
rickman

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