Zero operand CPUs

Write it in Forth. Also about a day's work. Use a PC Forth to generate code for it, and when you get it working set up a little "talker" for interactive debugging. You don't need a full Forth in the target for that.

We have several times managed low-level controllers (not quite "smart" enough to support a full Forth VM) that way.

...

Ah, well, that's a problem. If you can't get a detailed description of the instruction set, you're stuck.

Cheers, Elizabeth

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There is now a link on the instruction set page presenting an english text description of the BO instruction. All other instructions follow a similar symbology.

SU always has carry, BO always rotates through carry. DI leaves the carry alone, just like all the register/memory move instructions. All opcodes above 15 are subroutine call addresses. There are no general purpose register fields in the 4 bits of hardwired 16 opcodes (0-15), although there is some pattern to it.

Yes the indexing has been fixed, i.e. non-clocked assignment to indirect, which is also good for speed, as well as executing the current instruction rather than the current operation with the last instruction's indirection register. (this removes a row of clocked flip-flops).

Personally I find what else I have to explain as a difficult task. I would accept any correct documentation which falls under the BSD licence, or has no publication restriction.

The simplicity of the assembler was the main reason for the instruction choice, and lack of multiple addressing modes. In some senses the assembler complexity indicates how much decode processing is required for an instruction. There is a GPL assembler written in forth, using the gforth sytem this is suitable for macro programming. It's a tiny amount of code.

The lack of certain complicated instructions takes some working around, but it is not beyond a talented code writer. The macro feature is not really relevant, as a subroutine will work, but I suppose some critical inline macros would be useful to some to prevent excessive return stack juggling.

All instructions are fixed and final, except RE and SE, which are useful only in multi-tasking, and even then there is some debate.

cheers jacko

Sounds ok. I did think of using such a pick optimization, but considered it responsable for a potential cache slowdown as the design progresses. In nibz picking lower in the stack like this may be possible, but is not advised for scalability reasons. I have the idea too that any object C (++) should have method local instance variables only, indicating which method has write access to the variable. A tough restriction, but I think essential for scalable future coding.

True.

Yes , a good code density is possible. The use of code compression techniques by using an indirect jump vector table is a possible improvement in code density.

Thus the following memory types could be defined.

1. Microcode. 4 bit instructions wide memory.
2. Jumpcode. n bit < 16 bit (n->16 map addresses).
3. Fullwidth. 16 bit.

cheers jacko

Look at using a table driven user definable universal assembler

b. Farmer. (I am back).

So, are we going to see a Nano-Blaze for the 6-LUT Xilinx parts ? ;)

-jg

Dude, you are really terrible at this. In one place you tell people about a CPU you designed with no specifics. Another place you post a link to a web page with very fuzzy descriptions of the instruction set that is not usable. Then here you post that you have added some more explanation, but no link. Are we supposed to search around to find the link to your web page again? I have no idea where to find it.

I may not be very tactful, but I really am trying to help you, not be insulting. I hope it doesn't come off that way.

Rick

For perl, Open Perl IDE

-urb

I once wrote a microcode assembler *generator*. It would extract the operand specs from the Verilog HDL source and generate an assembler on the fly and then run it.

The only two hardcoded ops were "org" and "label". The program was quite small, less than 200 lines of Common Lisp code. The assembler was built on top of Common Lisp so you also got the powerful Common Lisp macros and functions as a free feature.

Petter

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Agreed wholeheartedly. The Transputer suffered badly because the technology that would make it effective (particularly, very fast serial links) was not available at the time; and the "prefix" mechanism was too wasteful of code space for comfort; but it had some brilliantly clever architectural ideas and I mourn its passing.

Context switches could happen only at "scheduling points"; I think there were more of these than merely conditional branches. But whatever the detail, the basic idea of choosing only to switch context when the stack is empty is very cool. It requires very tight coupling among architecture, compiler and runtime executive, though.

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This 3 level stack already covered a great deal of formulas to calculcate. There is also a one byte instruction to fetch one of

16 memory locations, probably located in on chip ram. You may think of those as registers, and below that as explicit microcoding.

The shallow stack of the transputer is lost on context switches for equal priority task. Together with the limitation where context switches could occur (only on conditional jumps) this accounts for a very practical design. (I would like to see a Ghz transputer with all the modern chip design tricks.)

Groetjes Albert

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I offer to write an assembler for euro 500 if it is of the complexity of an 68K, and for Euro 1000 if it is of the complexity of a DEC Alpha.

Now we are at it, would it not be a nice inroad for Forth if we were to generate the back end of gcc by Forth Assemblers? [My post-it fix-up assembler could be beefed up to do BEGIN NAME HASH PLONK REPEAT where NAME fetches the next word, HASH does a perfect HASH (and takes care of numbers) and PLONK is a single toggle of bits into memory. There is no conditional code, except for error checking. Now the output of a compiler can be trusted ... ]

Groetjes Albert

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You are so right... I looked (again) the nibz web

downloaded the most promising document (tagged FEATURED!)

did not understand much, scrolled to the end of the document.. where on the last line stands:

".... ummmm ...."

guess this is what we all should be doing: ummmmmmm

now, if we compare nibz to Mproz3

then

1 mproz3 is MUCH smaller 2 has superiour docu 3 has VERY simple assembler with source code (single file just invoke gcc to compile it)

mproz3 is now available in VHDL form, and succesfully working in Silicon Blue FPGA :)

so it doesnt matter how many times the nibz may be better, without documentation and tools its useless for anybody except the author.

Antti

Actually UNconditional jumps and lend (loop end). This was quite nice since you could prevent a context switch simply by

ldc 0; cj L

Andrew.

\ FORTH Assembler for nibz \ \ Copyright (C) 2006,2007,2009 Free Software Foundation, Inc.

\ This file is part of Gforth.

\ Gforth is free software; you can redistribute it and/or \ modify it under the terms of the GNU General Public License \ as published by the Free Software Foundation, either version 3 \ of the License, or (at your option) any later version.

\ This program is distributed in the hope that it will be useful, \ but WITHOUT ANY WARRANTY; without even the implied warranty of \ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the \ GNU General Public License for more details.

\ You should have received a copy of the GNU General Public License \ along with this program. If not, see

\ \ Autor: Simon Jackson, BEng. \ \ Information: \ \ - Simple Assembler

\ only forth definitions

require asm/basic.fs

also ASSEMBLER definitions

require asm/target.fs

HERE ( Begin )

\ The assembler is very simple. All 16 opcodes are \ defined immediate so they can be inlined into colon defs.

\ primary opcode constant writers

: BA 0 , ; immediate : FI 1 , ; immediate : RI 2 , ; immediate : SI 3 , ; immediate

: DI 4 , ; immediate : FA 5 , ; immediate : RA 6 , ; immediate : SA 7 , ; immediate

: BO 8 , ; immediate : FO 9 , ; immediate : RO 10 , ; immediate : SO 11 , ; immediate

: SU 12 , ; immediate : FE 13 , ; immediate : RE 14 , ; immediate : SE 15 , ; immediate

HERE SWAP - CR .( Length of Assembler: ) . .( Bytes ) CR

Antti - where did you find the mproz3 design?

My google searches consistently turn up ftp://137.193.64.130/pub/mproz/mproz3.zip, but this server appears to be down. Do you know of a mirror for this. Also, from what I've been able to read, this design was originally a schematic design. Did you convert it?

How does it compare to picoblaze in size, execution speed, and code density?

-Urb

Jacko, if you want other to understand, please make simple example:

1) test source file: TEST.ASM

=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D

inset asm op codes to write value 0xAA55 to IO address 0x2233 here

=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D

2) provide some executable file such that:

jackocompiler.exe TEST.ASM >TEST.BIN

produces a code ready to load into FPGA block ram and when executed will write AA55 to address 2233

saying this is part of GForth... so what is ? you are part of GForth? nibz is? your assembler is?

looking at your 2 LETTER code style, i have hard times to understand how to

MOV OUTPORT, DATA

we all belive what you do does makes sense for you but for others to use, ? no docu, no examples, no use..

eh i read you donation record, 0.00 so far eh my paypal account is at 0 too, otherwise i would donate the 42$ what i did estimate to be your total earnings...

you do not need to try to rush so much, just do something properly....

B16 is also stack based soft-core, but it HAS an assembler please take a look, look how others have done assembler for stack machine, its ok to look, you dont have to todo everything from scratch

Antti

What do you expect from something that does not need operands or has only the operand "0" zero? It can not do much useful things - ok, it could heat the room it is inside. The purpose of a processor is to combine operational procedures with one or more operands. It does these operations one by one. If the CPU gets zero operands at all, it's very simple to make it high speed or space efficient. It could be targeted by every language that has a NOP operation.

I know, I do understand this in the wrong way, but it had to be told anyway.

Regards,

-Helmar

a e

oz3.zip, but this server appears to be

t?

ty?

speed LOWER code density WORSE

but: resources LESS addressing space LARGER

the FTP seems to work and the VHDL translated version is now available, just uploaded

cheers Antti

The umm does make sense in terms of what the document was describing.

There is now a featured download of the instruction set at

And has a self modifying code tendancy.

Excellent.

In general true.

cheers jacko