Hi. I'm an undergrad student & we're designing an 8051 core, for an FPGA. Most of the cores i saw, have multiplexed the port and ext memory interface signals, as is the case for an 8051chip.
I want to make separate ports for IO & ext mem, as it will simplify my design. Please tell me the tradeoffs for this.
In general, why do you need to multiplex signals for a core? finally, it's going to be used to make some sys. on-a-chip ,right?
(I'm a beginner at digital design)
Thanks. Neha
The historic reason for using multiplexed buses was to have as few as possible pins on the chip's package. The fewer the pins, the cheaper the device.
If you design for system on a chip, there is no special need to multiplex anything, as long as your wiring does not get insanely complex so that you don't run out of resources, and you don't use up pins on the FPGA, if you need to lead your processor's pins outside the FPGA.
Modern FPGAs can have lots of pins you can use, so you should have no problems with demultiplexing buses for a small 8bit design like 8051, but it is best to check your FPGA and board manuals to be sure.
f
They do that to 'match' the original cores operation, so it can drop-into as many designs as possible.
Two things are multiplexed :
a) P2 shares with A8-A15, and that can matter if your code uses PDATA [MOVX @ Ri opcodes ] If you never use PDATA, you can move P2 to other pins.
b) A0-A7 shares with DB0-DB7 - there is no SW impact of this, but some peripheral devices have ALE pins, and so expect the sharing, and will not work with non-mux bus. If you never use ALE peripherals, then you are probably OK to move A0-A7 to other pins.
-jg
Have something to add? Share your thoughts — no account required.
Ask the community — no account required