what does the baudrate of DMA depends on ?

Quite a few factors, some of which are:

a) The DMA / bus latency itself - i.e. how long it takes for a DMA cycle to run from the time the DMA Request line is asserted. This is usually a function of the CPU / Bus Arbiter / Instruction types.

b) The data bus width - particularly as it applies to a DMA cycle. This is further influenced by the bus width of the peripheral device, and whether it supports some form of data aggregation, eg. a FIFO.

c) Yes, the clock speed AND bus cycle length - i.e. the number of clock cycles to complete a bus cycle.

-- Cecil Hill

Hi Cecil Hill, Thank you very much!!!

Possibly.

Possibly.

And you missed quite a number of other possible influences.

Your question is really a *lot* too vague to allow a precise answer.

DMA on what platform, used by which peripheral, in which circumstances?

Not to mention that the term "baudrate" is applicable to serial comms, and inapplicable to DMA.

Steve aka pedant of Selsey