^ This showed up some latencies here. It took about two minutes to figure out that your intent was "know". Something about well worn internal paths :-)
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Chuck F (cbfalconer@yahoo.com) (cbfalconer@worldnet.att.net)
Available for consulting/temporary embedded and systems.
USE worldnet address!
If 4 or less comcurrent TCP/IP connections is good enough, then the Wiznet W3100A is a nice device. It runs the TCP/IP stack in hardware, hence the amount of code to write for a TCP/IP connection is quite simple. Also because it handles the TCP/IP, the AVR is only bothered when a packet destined for it's node has been received. They also have a number of modules available that includes the W3100A IC, together with the phy-chip and the magnetics + connector.
I don't think that is true. We are using the 91c111 on an 8 bit bus (the processor can do up to 32 but we need the other 24 pins ad I/O). You can attach both halves of the 16 bit bus to the same 8 bit processor bus (bit 0 = bit 8 etc.) and program the 91c111 to only send/receive 8 bits at a time. This does not work if you want the fastest DMA transfers since these are only possible on a 16 bit bus but should work for normal processor I/O and 8 bit dual address DMA.
I was just wondering if anyone had been able to get small quantities of SMSC parts and where from? I tried the local rep a while ago, but the minimum quantity was too high; 360 from memory for a multi-io chip.
Here in the US it looks like I can order 1 of the LAN91C111NC from Nuhorizons for $24. Sometimes when you try to order small quantities, only then do they tell you about minimums. Can you order on the web from the US?
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Rick "rickman" Collins
rick.collins@XYarius.com
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A 12.5 persent increase in throughput achied by increasing the bandwith by a whopping 900 (in words: nine _hundred_) percent. Which, as as other posts in this thread confirmed, may well have come with a
200 percent penalty on the energy consumption. Unless the application very strictly needs exactly those 100 kByte/s, that's about as good an example of wasted resources as any.
Actually, that increase in overall throughput is quite likely not even caused by the increase in bandwith, but rather by the lower latency of the line.
How much more?
That's not exaclty a new question. Not in the context of this thread at least. The assumption from early on in it was that the micro almost certainly *won't* be able to do anything useful with the additional bandwidth.
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Hans-Bernhard Broeker (broeker@physik.rwth-aachen.de)
Even if all the snow were burnt, ashes would remain.
A 12.5 persent increase in throughput achieved by increasing the bandwith by a whopping 900 (in words: nine _hundred_) percent. Which, as as other posts in this thread confirmed, may well have come with a
200 percent penalty on the energy consumption. Unless the application very strictly needs exactly those 100 kByte/s, that's about as good an example of wasted resources as any.
Actually, that increase in overall throughput is quite likely not even caused by the increase in bandwith, but rather by the lower latency of the line.
How much more?
Well, it's not exactly a new question. Not in the context of this thread at least. The assumption from early on in it was that the micro almost certainly *won't* be able to do anything useful with the additional bandwidth.
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Hans-Bernhard Broeker (broeker@physik.rwth-aachen.de)
Even if all the snow were burnt, ashes would remain.
12 Mbpb, form a short guess. I should also note, that the ATmega is currently running at 14,7 Mhz. Overclocking at
18 Mhz should be possible and there may be faster chips available in the near future. No idea, if faster 8-bit micros are available from other vendors. What I wanted to say is, that the 8-bit micros already reached the limit and will pass it sooner or later.
One idea that came up in the Ethernut mailing list was, to use a CPLD for DMA between SRAM and the NIC. That would free the CPU from the main workload.
Harald
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