[Q] Old PC-ISA Data Bus Hold Time Requirement??

Markus,

It looks like the minimum would be 121ns (1 bus cycle @ 8.33MHz for a

16-bit memory read; longer for 8MHz or 4.77MHz buses). The typical ISA duration can vary a lot by the circumstances, from 1.5 bus cycles to more than 4.

ISA peripherals can be pushed much faster if you design to their product specs instead of ISA timing. For example, an RTL8019AS Ethernet controller has a response time of 60ns.

In the other direction, the IORC minimum can be extended greatly if the peripheral asserts the CHRDY signal - this should happen in the first

125ns, and IORC must be extended until it's de-asserted. (You will run into problems if you make IORC too short and ignore the CHRDY signal.)

FWIW, this info is covered in the Mindshare book ISA System Architecture, which is well worth the money. It's notably missing a table of electrical specs, but it does cover it in the text and timing diagrams.

For curiosity, why are you asking? Are you trying to access an ISA peripheral, or is you device a peripheral going into an ISA PC? What problem have you run into?

ISA-bus information is virtually non-existant these days. This is bad for anyone making PC/104 boards since that spec does not contain any timing related data, but used to refer the user to the IEEE P996 spec which has been deleted. I tried to find the IEEE P996 draft spec, but could never find a copy. The only remaining source of info with any great detail is the book by Edward Solari, "AT BUS DESIGN". I think this was always the definitive reference and is the only one at this point.

My philosophy is to provide lots of setup and hold time since you never know what spec the other devices are designed to. Since modern logic is faster than the logic used in the original ISA bus designs, a state machine running at 4 or 5 times the actual bus rate can do a very good job of providing adequate timing tolerances.

If there are any specific timing values you need, I can look them up for you.

It appears that the hold time from rising edge of MEMR- or IOR- is 0 min. The setup time is spec'd from the falling edge of MEMR- or IOR- or rising edge of IOCHRDY and varies depending on the type of cycle.