Dear All,
I am working on Xilinx EDk and microblaze. I am facing some problems while downloading my .bit file onto FPGA. Sometimes FPGA is programmed successfully and sometimes it fails. Are some other people facing such problem? What might be the possible reasons? Somebody please advise me...
Azam
"mazamshahid" schrieb im Newsbeitrag news:f6KdnZ7UIM9d_vLUnZ2dnUVZ snipped-for-privacy@giganews.com...
Parallel Cable IV is BS.
Only every second download or other PIV cable function in EDK is successful.
The USB cables work as advertised.
For FPGA issues you'd better use comp.arch.fpga.
MIKE
-- www.oho-elektronik.de OHO-Elektronik Michael Randelzhofer FPGA und CPLD Mini Module Klein aber oho ! Kontakt: Tel: 08131 339230 mr@oho-elektronik.de Usst.ID: DE130097310
It works fine if you cut the data clock rate to something less than
1MHz. I vaguely recall a 250kHz option or something close to that, which takes a bit of fussing to figure out how to set it (I use Impact with an older version of Webpack, since the new versions are pathetically huge).-- _____________________ CRC crobc@REMOVE-THIS.sbcglobal.net SuSE 10.3 Linux 2.6.22.17
I had the same problem. Turned out in the end to work fine provided I first unplugged the power from my laptop so it was running on battery power only. Unplugging the power makes the CPU clock speed half, so I guess this is the issue.
-- Regards, Richard. + http://www.FreeRTOS.org Designed for microcontrollers. More than 7000 downloads per month. + http://www.SafeRTOS.com Certified by TÜV as meeting the requirements for safety related systems.
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