Hello, All! I'm experimenting with interrupt latency on a Motorola ColdFire 5272 and the timing is not very satisfactory. I have a device connected to an external interrupt line #2 (or #3 - configurable with jumpers). I have put a few commands accessing chip select 3 in order to connect to those lines and see the timing on a scope. The interrupt is of the highest priority and the ISR does not use any of the kernel services (uC/OS-II) - it doesn't even comply with uC/OS-II format of interrupts as there is nothing (short of reset) that can, in turn, interrupt it. The time interval between the interrupt line going down and the ISR marking its entrance with CS3 access varies between 1uS up to 10+uS, even though there are only LEA -60(A7), A7 (adjusting the stack) and MOVEM.L D0-D7/A0-A6, (A7) (saving the generic-purpose registers) commands before accessing chip select 3. There are no other interrupts of that priority (6) in the whole system, and OS_ENTER_CRITICAL() macro was rewritten to mask all interrupts up to level 5. I would expect the whole prologue to take less than 500 nano-seconds, given this setup. What can be the reason for such a slow reaction? Are there any instructions on this processor that can take so much time?
Thanks in advance, Arkady.