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Green Arrays Board Level Design

Green Arrays is building chips of asynchronous processor arrays.

"Varying capacitor values create impedance peaks as well as nulls in the frequency domain and should be avoided."

This is in the data sheet for the GA144 device. I am sure it is well intentioned and I am sure the folks at GA know their chip, but I don't think this advice is what I would hear from various board design experts.

In a class I took some time ago with Lee Ritchey, he showed how using multiple values of caps in the power distribution system (PDS) will provide a lower impedance across the board... in spite of the impedance "peaks" caused by the resonances of the cap and parasitic inductance. These peaks are mitigated by the equivalent series resistance of the caps. They still exist, but in a well design system are lower than the impedance at that frequency if only one value of cap is used. Lee never showed an example where he was trying to lower the PDS impedance at only specific frequencies.

The authors of the data sheet seem to feel designing a PDS with a low impedance over a broad bandwidth is important for the GA chips moreso than in In a system where the noise frequencies appear to be fixed. I doubt that anyone targets specific frequencies when they design a PDS. After all, most systems use multiple frequencies and a board designer isn't going to want to respin a board because someone changed the frequency of the oscillator.

Any comments on the likely validity of the GA recommendation to use a single value of ceramic cap rather than multiple values?

One of the things from Lee Ritchey's course that has stuck with me is when he reported a conversation with an FAE where Ritchey was told that if he didn't abide by the advice in the app notes (which Lee was disagreeing with) that they wouldn't guarantee he board would work. He asked if he did abide by the app note advice, would they then guarantee that he board would work? I suppose not... eh?

Rick

Reply to
rickman
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Post this to the si-list (where Lee Ritchie is subscribed) if you want to initiate a lengthy discussion on the topic :-).

Most likely you will be advised to buy a $30k+ simulation package to simulate your board :D.

But there are people there who do know interesting details of high speed PCB design there, no doubt about that.

Dimiter

Reply to
Didi

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Where would I find the "si-list"?

Rick

Reply to
rickman

It sounds a little mangled to me. Half correct. Impedances are in PARALLEL, so peaks are naturally removed.

IIRC Infineon did a good study on this a while back, with measured plots.

The single most dominant Power Supply Impedance driver is the Ground plane, which does most of the High frequency work, then the Inductances from the traces to GET to the plane, and then last is the capacitor values. Physical size matters too, as that can determine lead length, and how close you can get a cap to the chip. Then if you do Via-In-Smd, you will have even lower inductance...

If you have an EMC fail, at a specific frequency, then looking for a null there could make sense, but otherwise, other factor are much more important than Cap Value.

-jg

Reply to
Jim Granville

I don't think that is quite right. The peaks are there. This is a result of the parallel combination of one cap looking capacitive and another cap looking inductive. This shows quite clearly in simulations as well as measurements. But there is also the effective series resistance of the cap which disrupts this resonance and greatly reduces the size of the peaks. A theoretical LC circuit will have infinite impedance at the peaks. A real LC from power supply caps will have peak heights the same order of magnitude as the individual devices.

My real point is that I have never seen a designer consider the specific frequencies of a circuit and try to match the nulls to those frequencies. I think there is far too little control over the details that determine the locations of the peaks and nulls to be able to do that (the parasitic inductance and even the capacitance). So all power distribution systems are designed to have low impedance broadband, not at specific frequencies. I just found this note to be such an odd thing to include. It makes me wonder how well connected the author is to mainstream board level design. Or maybe I should wonder how well connected I am to mainstream board level design? :^*

Rick

Reply to
rickman

Is that the Signal Integrity list?

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-- Roberto Waltman

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Reply to
Roberto Waltman

Thanks. I think Lee mentioned this in his class and how every so often in that list someone will have a long discussion trying to contradict some of the points he was making in the class. I hope I'm not the next one...

Rick

Reply to
rickman

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