FPGA power optimize! Help!!!

Hi all I have designed some FPGA based applications but very simple ones. Now want to find some methods/algorithms in FPGA design to optimize power. search many documents (IEEE,..) but they are not in detail. I need som free documents and open source (or only detail steps) to implement powe optimize algorthm. So i hope somebody can help me with useful links!


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Are you looking to optimize the firmware for a given FPGA to minimize power, or are you looking to design an FPGA chip with power optimizations? You'd only be doing the latter if you were a student specializing in IC design, so I'll assume the more likely former case.

This sort of thing is highly dependent on the particular chip you're working with. The first place you should look is on the web sites for your FPGA vendor -- if power is the most critical parameter in your design, I'd start by choosing the FPGA that seems to be the best supported by it's vendor.

In general you want to keep the clock speeds as low as you can, and to "flip" the fewest gates possible every second. Having an FPGA that's optimized for power consumption will help; FPGA architectures tend to tickle more gates than you think, so you'd need one that's specifically made not to. Until a decade ago no one cared at all whether their FPGA's consumed lots of power as long as they were fast and flexible; even today many FPGA users put power consumption low on their list when they're selecting chips.

Good luck. It sounds fun.

Tim Wescott
Control systems and communications consulting
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Tim Wescott

Just one more thing. Some FPGA are grouped in blocks for power, so you can select your logic to minimize active power use. Just a little more planning in laying out your pins, rather than letting the software to do it all.

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FPGAs are used in embedded systems, so your questions are certainly appropriate for this newsgroup. But you are likely to get better answers to FPGA specific questions by posting to comp.arch.fpga. That group is frequented by FPGA geeks and tech reps from the various FPGA vendors, and they often provide very knowledgeable information.

Techniques to reduce power are very dependent on the specific part you are using. You should go to the vendors website, look up the part you are using, and look for whitepapers and tech reports on how to minimize power consumption. For instance, you can go to

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and type "low power" into the search box, and get oodles of links.

Here is some general advice:

  1. Use a part that is designed for low power. Such as Coolrunner, or Spartan-3L series. Altera, Lattice, etc. also have parts designed to minimize power.

  1. Use the part with the lowest gate count that your application will fit into. This will minimize power, but it will also take away some flexibility to add features or fix bugs.

  2. Run your application with the lowest clock freq that you can.

  1. Try to trim down and simplify your application. For instance, most FPGA designs include a global reset, but this is rarely necessary.

  2. If you really know what you are doing, you might be able to save some power by gating you clocks. But this is considered a very bad design technique.

  1. Are you really sure you need an FPGA? If a microcontroller, such as an ARM or AVR is fast enough to run you application, it will probably use considerably less power than an FPGA.

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