Hi Everyone
In the case of a simple configuration comprising a CMOS microprocessor plus one external CMOS SRAM, it may well happen that the processor's external bus interface becomes inactive for long periods (for instance, when the uP is accessing code and data in internal memory).
In this case, the bus is high impedance, and could, in principle, float to a voltage mid-way between the power rails. This would cause both p- and n-channel devices of any CMOS input buffer connected to the bus to partially conduct, resulting in increased dissipation and possible device damage. Are devices designed to be connected to data buses somehow protected against this problem, or should the bus be pulled up or down with resistors?
TIA Geoff