I don't understand points 2,3,4. In the Harvard Arch, we separate code and data flow. Eg: LDI R16, 0F
0F is pulled from flash (using the data bus - operand) at the same time as the LDI (via the code bus - opcode). The register R16 is GPR so it's in the CPU.What the heck is 2 for: 'a set of address buses for accessing the data' ? And the others: a set of address buses to access the opcodes
Why do we have: In RISC processors, there are four sets of buses
RISC processors have separate buses for data and code. In all the x86 processors, like all other CISC computers, there is one set of buses for the address (e.g., A0?A24 in the 80286) and another set of buses for data (e.g., D0?Dl5 in the 80286) carrying opcodes and operands in and out of the CPU.
To access any sec-tion of memory, regardless of whether it contains code or data operands, the same address bus and data bus are used.
In RISC processors, there are four sets ofbuses: (l) a set of data buses for carrying data (operands) in and out of the CPU, (2) a set of address buses for accessing the data, (3) a set of buses to carry the opcodes, and(4) a set of address buses to access the opcodes. The use ofseparate buses for codeand data operands is commonly referred to as Harvard architecture. We examinedthe Harvard architecture of the AVR in the previous section.