Hi,
in a computer science class we were discussing the RISC and used the MIPS ISA with the SPIM simulator for some practical labs. The SPIM simulator had the calling convention that registers $t0-$t9 were caller-saved while $s0-$s7 were callee-saved. So, here the division in these two classes of registers was static.
Another example are Infineon TriCore microcotrollers. They do not use caller-/callee-saved registers but with each call the upper context (consisting of some particular data and address registers) is automatically saved and restored with a return instruction. Thus, here an explicit division of registers across calls is not given.
My question is now what is the common practice for today's embedded system processors? Do they provide some unique memory subsystems for a fast context switching (like for the TriCore) or do they support the traditional way of a strict division of registers into callee-/caller-saved registers? If so, who defines which registers should be used for which purpose? Is there one particular calling convention for each processor people working in a shared project must strictly follow?
Regardas, Tim