Hello All
I am currently working on a design in which I have to perform a 32 bi convolution. Can anyone give any ideas of doing this with maximum paralle processing so device utilization is minimum??
Thank You.
This is a near-null question, which invites flippant answers. You have so few constraints on this that all answers are absurd.
"Maximum parallel processing" and "device utilization is minimum" conflict, unless you mean time minimization. So the clear answer is that for an N-point convolution you need N^2 multipliers and N^2 adders, and you will be able to get your entire answer in one step (although perhaps not one clock cycle if you don't pipeline).
OTOH, if the device utilization is what really needs to be minimized, then you need to do the convolution one bit at a time, and take, I dunno how many clock steps to do the math, but you'll only need on the order of
64 * N bits of memory to do it.More detail from you will enable better answers from us, and posting this to the FPGA newsgroup my lead to better answers yet.
-- Tim Wescott Control systems and communications consulting http://www.wescottdesign.com Need to learn how to apply control theory in your embedded system? "Applied Control Theory for Embedded Systems" by Tim Wescott Elsevier/Newnes, http://www.wescottdesign.com/actfes/actfes.html
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