Simple amplifier: simulation & real world do not agree

If you want a higher-amplitude square wave of the same frequency, what you want is to configure the transistor as a switch, not as a linear amplifier. In other words, the transistor should be operating at either saturation or cutoff, such that the peak voltage of the resulting square wave will be set by the supplier (minus any drop resulting from the collector resistor), and the low will be set by whatever voltage is dropped by the transistor in saturation.

Bob M.

This doesn't have a lot of gain to start with, and capacitances will gobble up that fast.

If you reduce all the resistor values by, say, 10:1, your hf rolloff frequency should increase by almost that ratio.

John

I suggest you simplify your circuit to make it more of a switching output than a linear amplifier. TTL sources generally are a lot better at pulling to ground than they are at pulling up to the positive rail. So you might try eliminating the input capacitor, lowering R1 to about 470 ohms, get rid of R2, and R3, short out R5 and possible lower R4 to between 1k and 4.7k. This should give you a fast, full output swing.

Accurate simulation takes alot of skill and experience. You dont need an amplifier just a level shifter, look up "clamp circuit".

you have in circuit capacitance problems, most likely the lay out of components with the high valued R4 and R5 your using or the CMOS input device has high cap and you must over come it.

you could increase the performance a bit by place a by pass cap parallel with R5, something in the neighborhood of .1 (100n) might do... but still your dealing with surrounding capacitance in my opinion. that is why board design is so important when it comes to this like this. just a thought..

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Real Programmers Do things like this.
http://webpages.charter.net/jamie_5

Big problem is the transistor base-collector capacitance, being 'multiplied up' by the voltage gain of the amp, (Miller effect). So ... you've say maybe 10pF for that 'Ccb' and you've a voltage gain of about 5, so the Ccb now acts like it's 50pF.

Doesn't seem a lot but problem is that from the input signal point of view, this 50pF is in series with that 8k2 resistor and makes a nice low pass filter. In this case it causes the input signal to start rolling off at about

0.5MHz.

Also ... if you connect to your CMOS counter with a foot or so of screened lead (equivelent to say 30pF) then you've yet another low pass filter at work but this time it's the 12k collector resistor driving the 30pF (also runs out of steam at about 0.5MHz!).

So ... Easiest path is to drop the circuit resistances and force the frequency rolloffs to increase upwards pro-rata. (Be prepared to give up a few more ma.)

Eg make R4=1.2k, R5=220, R1=1k. Circuit should run 10X faster.

(it may though have been better to have made it a straight 'switching' circuit in the first place) john

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This is almost word-for-word what I was going to say, but I'd add a speedup cap across R1.

Do I win a prize? ;-)

Cheers! Rich

Fine by me.

I think so. How would it be possible to get a nice 0-9V output from the OP's topology, at all? The quiescent current through collector and emitter resistors alone makes this issue stand out to me. It's a degenerative amplifier, for gosh sake.

Jon

Indeed. The fixed 1.5V pedestal is acceptable for driving a CMOS logic low but pointless to specifically design out, when a simple switch works much better. Been oh so so long, I had to mug up on TTL. Those logic lows look annoyingly close to the 0.6V input for a switch transistor, so slightly modded the drawing supplied earlier (who's is it?). (Anyways, thought TTL had perished a 1000 years ago!) john VCC

5V | | .-. .-. | | R4 | |1k | | 2K2 | |pullup '-' '-' | | o----- out | R1 1k | +----||----+ .-. | cap: ~100 pf. | | | | | === '-' GND | 470 pulldown === GND

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John Popelish a =E9crit :

That's what I did in the first place, except that I had picked 4k7 for R1, but the output stuck low all the time. I thought that maybe the transistor had problems of coming out ot saturation (is that why you suggest such a small R1? *) so I tried a simple amplifier to stay out of saturation. The shape of the output was not really a concern as long as it would swing from about 2V to 8V.

• I am from the opamp generation and I am trying to improve my transistor skills, that's why I am playing with this.

Thanks, Jenalee K.

john jardine a écrit :

Or if he doesn't need inverting the signal:

+9V _ | .-. | | | |2K2 '-' | | +--->

| ||-+ ||-+-||-+ | | .-. | 2K2| | | | | | '-' | | | from TTL >-+----'

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Thanks,
Fred.

Hmm. Staying with the degenerative amplifier and in keeping with your suggestion that as little as 2V is okay, you might try this:

I haven't wired it up, but I think it should be about right.

You could dump R5 (short it) and C3 (remove it.) Won't work quite as well, but might be fine.

Quiescent current is set at 1mA.

If you need explanations, I can walk through your questions, I think.

Jon

That tels me one of two things were happening. Either the stored=20 charge in the base did not have time to drain during the input low=20 periods, or the input was not really TTL level. TTL outputs typically=20 pull down to a small fraction of a volt above ground, if they are not=20 sinking significant current. A lower value base resistor allows the=20 stored charge to drain faster through the small voltage drop across=20 the resistor (.6 volts at the base and, say, .25 volts from the TTL=20 source). The base drive would be excessive during the logic high=20 state, except that TTL outputs do not pull up well, above about 2.5=20 volts, so it isn't so bad, unless you need the source to also drive=20 some other input at a larger voltage swing.

What, exactly is the signal source for the transistor? Have you an=20 oscilloscope to measure it and other nodes during operation?

Understood. The problem may not be with the transistor, but with the=20 signal source.

Here is another approach for you to play with. Use the transistor as=20 a common base amplifier (voltage gain, but no current gain, and non=20 inverting). Tie the base to the center node of a resistive voltage=20 divider made up of two 10k or 4.7k resistors tied between +5 and=20 ground. Connect your signal source to the emitter and connect the=20 collector to a 4.7k or 10k pull up resistor to the 9 volt supply (or=20 whatever voltage is the positive rail for th CMOS chip).

When the TTL signal is positive, the base-emitter junction is reverse=20 biased, and the collector pull up resistor provides a full positive=20 output. When the TTL input pulls down to almost zero, the=20 base-emitter junction is forward biased (with the base current limited=20 by the divider total resistance) and the transistor saturates on,=20 pulling the output down to the TTL low voltage plus the transistor=20 saturation voltage. You lose some of the TTL pull down current=20 capability into the base divider, but you get more voltage swing than=20 the TTL signal delivers.

Try this, both because it will work, and because it's sort of interesting...

John

John Popelish a =E9crit :

Good question. I was driving it with an old crystal oscillator (Kony KHC1100 1MHz) that I had found somewhere and I supposed it was TTL. But I can't find any information on it, except that it is apparently obsolete, and so it may be an HCMOS device.

And yes, I have access to a good oscilloscope.

I will try your suggestions as well as those from all those kind other repliers. I will also try with different signal sources so that I do know for sure what kind of driver I have.

Thanks, Jenalee K.