Second Stage of Op-Am (Current to Voltage)

First off, look at the piss poorly posed questions in my other subthread with the OP. He gave Ic1 - Ic2 = Iout negative as the condition, and wants to know where the negative Iout is going to come from - then my answer is that it ain't. For all I know Intuitive ICs for Telemarketers would've skipped the initial condidtion of the cap prior to that state, so forget that. I couldn't assume that on page x where he's still blabbering about a DC condition like Ic1 - Ic2 = Iout, that he's also talking about a steady state condition where Cc *might* be obliging and supply some reverse Iout.

So where's the AC generator anyway? None drawn nor mentioned.

Q4 can't go below Vee (+ Vce_sat) and that's what the emitter of Qmiller is connected to. If you *could* go below Vee to *try* to draw current from Qmiller, Qmiller would be reversed biased.

Yup.

Bull! It's a gain limiting term.

That's differen't from what the OP was asking (look at the OP) and as I said, it's an effect of Cc - that may or may not manifest, BTW, like you said. You mean slewing. That's not the same as the condition given i.e., Ic1 - Ic2 = Iout negative.

Virtually all 741 op-amp schematics that I've seen are differential amplifiers with current mirror active load. Not sure why you need to be so specific for general theory of operation. Is there a 741 that deviates significantly from this? I wasn't expecting your response to be different that your other posts. The components are not screwed around for fresh eyes to my question.

Can't speak for Larry, but I am and so are several texts and lectures.

I was looking to understand the op-amp analytically - not plug and chug root finding in SPICE. I want an articulation as to why it works - not "it just does" or "what else could it be...", "where else could it come from" - heard those a million times. Simply put... please prove it - analytically. So far it doesn't seem you're defending your position very well - or rather at all. That's why you're "repeating" yourself. "SPICE says Iout can't be negative" fine - then please explain/prove why (analytically using dc-analysis or small signal analysis) or point me to some text that can.

Please refer to "Intuitive IC Op Amps" on page 14.

I believe that Iout can't be negative in the steady state because there isn't a source of current other than leakage through the output transistor. Current in the positive direction will flow through the diode in the output transistor.

However, the current never has to go negative to control the output. It simply has to control the positive Iout appropriately (which in turn controls Vbe, in a way that depends on beta), and work that against Io. The output can vary between -Vee + Vbe and Vcc simply by controlling the base current.

Nope and if you were following the threads, you'd know that the circuit OP linked to has a follower *and* a CE stage for the miller stage with a 100 ohm resistor on the emitter of the CE stage. So if beta were 100 that's Rin of 1 Meg. Sorry, I never shifted gears back to the figure below. Big difference.

So what the expression can be negative? Leave it there until the cap is done discharging and tell me where the current will come from.

I still do as long as we're not trying to get bidirectional flow from the base of a bjt. If the cap (even the b-c cap) pumps current that way sometimes, that's a transient response. After that, the diff stage can ask for as much as it wants and if it could go below the rail, it'd keep doing so until the b-e breaks down in reverse.

I've updated the schematic to give the nameless transistor a name. Qout's emitter is grounded w/ intrisic resistance of ~X/Ic plus the output collector voltage is being balanced with current source to achieve the high VOLTAGE gain(see below about active loads). The base voltage is determined by the differential amplifier current mirror active load so Vo' is not pinned. Your naive application of a diode drop is no longer relevant and for the most part not used in much of the core design - except the output stage and support circuity. We're in Ebers-Moll/Mextram land now. Plot Vo' on SPICE - it's not pinned and is determined by the differential amplifier not (ground + Qout's Vbe). You could argue what you really meant is that Vbe is pinned indirectly calculated by the differential input stage. You're not that clever and your causality is screwed up. Qout is a high input impedance and high gain stage. Please skip the tangent on poles...

No.

What part of analytical don't you understand? Found my answer that explains the relationship between the op-amp's stage 1 & 2 rather well,

Possibly here, but I've only briefly looked @ it. You've actually been helpful for once. You're magic SPICE demo prompted me to get a free SPICE simulator - not that I'm fond of simulators. See circuit below.

Rails, saturation, poles, version of 741, etc, relevant to the derivation? I don't think so. If you read my other posts, I ultimately wanted to get a derived transfer function so I could see - though the process of derivation - the interplay between stages 1 & 2. I also asked if (V+ - Vi) was transduced to 1.) high impedance voltage source or 2.) bi-directional current source. All that other pedantic BS you were talking about - wasting other's time - can be analyzed/factored later.

In Frederickson's "Intuitive IC Op Amps", I was taking him @ face value that Iout = Ic2 - Ic1 ie: Iout can be made up externally & be bi-directional. This is what your learn in DC analysis of two differing current sources flowing in series & an output line - the delta is made up through a load on the output line(as long collectors are in linear active region). Since this is where the Iout controversy exists - I needed to reevaluate how the stage

1 - differential amp w/ current mirror active load works(DACMAL).

It's true that if the load impedance on Iout is "just right", the collectors Q2 & Q4 are in the active region & Iout = Ic2 - Ic1 is true and so is the possibility of its bi-directionality. However, where I went wrong is that I ignored output impedance @ Iout. It's absolutely not "just right". It's actually very large and the current is unidirectional. In this configuration, the transduction of (V+ - V-) isn't to current- ie: Iout - but rather voltage something like Vo' = A(V+ - V-). Horowitz & Hill in the "Art of Electronics" said the output impedance of the DACAML must be high - and treated it as a voltage source output not current. They also mention the gain of this configuration to be 5000+ (early 80's text).

Using SPICE, if one input is grounded and the other input allowed to sine oscillate the output voltage Vo' is virtually a square wave under transient analysis. If the input is made small enough, the output is replicated & scaled by virtue of operating in the square's transistion region. The phenomena being manipulated in the DACAML is the transistors' balancing of collector voltages(between saturation) of Q2 & Q4 to try and make up unobtainable collector current deltas. The modelling goes beyond using simple constant value transistor diode drops and beta.

Looking @ Leach's analysis, negative Iout(V+ - Vi) can exist (differentially - not absolutely - by superposition) wrt to the capacitor and that Qout serves as a high input impedance voltage gain. Removing the cap from the SPICE simulation still works(as you claimed) - though impacting AC performance. Again in an ac small signal sense, it's not really incorrect to view stage 1 as tranduction of V+ - Vi to current Iout - as Fredericken claims.

As a layperson - trying to learn how the basic op-amp works internally - I missed his point and took it literally in DC - but it seems to have eluded you as well.

Regards my Argumentative Jargon Laiden Lad,

Monty

+Vcc +Vcc o o | | | | 2 Ic = Bias Current Io = Bias Current | | | | | | o------o-----o | | | | |< >| o-------o----o Vo Vin(-) -| Q1 Q2 |- Vin(+) | | |\ /| Cc --- o |Ic1 Ic2 | --- | | | Vo' | |/ | o----------------------o---o-| Qout | | Iout |>

| | o | | | | | Ic1 | | o | | |/ | o----o---o-| Q4 | | | |> | | | Ic1 o | | o | | | |/ | | |--| Q3 | | |> | | | | | -------o | | | | | -Vee -Vee (created by AACircuit v1.28.4 beta 13/12/04

I need to make a correction it is (-Vee + Qout's Vbe) not (ground + Qout's Vbe). Damn split power supplies. Change is included along w/ few mods.

Monty

===============================

I've updated the schematic to give the nameless transistor a name. Qout's emitter is grounded w/ intrisic resistance of ~X/Ic plus the output collector voltage is being balanced with current source to achieve the high VOLTAGE gain(see below about active loads). The base voltage is determined by the differential amplifier current mirror active load so Vo' is not pinned. Your naive application of a diode drop is no longer relevant and for the most part not used in much of the core design - except the output stage and support circuity. We're in Ebers-Moll/Mextram land now. Plot Vo' on SPICE - it's not pinned and is determined by the differential amplifier not (-Vee + Qout's Vbe). You could argue what you really meant is that Vbe indirectly influenced by the differential input stage. You're not that clever and your causality is screwed up. Qout is a high input impedance and high gain stage. Please skip the tangent on poles...

No.

What part of analytical don't you understand? Found my answer that explains the relationship between the op-amp's stage 1 & 2 rather well,

Possibly here, but I've only briefly looked @ it. You've actually been helpful for once. You're magic SPICE demo prompted me to get a free SPICE simulator - not that I'm fond of simulators. See circuit below.

Rails, saturation, poles, version of 741, etc, relevant to the derivation? I don't think so. If you read my other posts, I ultimately wanted to get a derived transfer function so I could see - though the process of derivation - the interplay between stages 1 & 2. I also asked if (V+ - Vi) was transduced to 1.) high impedance voltage source or 2.) bi-directional current source. All that other pedantic BS you were talking about - wasting other's time - can be analyzed/factored later.

In Frederickson's "Intuitive IC Op Amps", I was taking him @ face value that Iout = Ic2 - Ic1 ie: Iout can be made up externally & be bi-directional. This is what your learn in DC analysis of two differing current sources flowing in series & an output line - the delta is made up through a load on the output line(as long collectors are in linear active region). Since this is where the Iout controversy exists - I needed to reevaluate how the stage

1 - differential amp w/ current mirror active load works(DACMAL).

It's true that if the load impedance on Iout is "just right", the collectors Q2 & Q4 are in the active region & Iout = Ic2 - Ic1 is true and so is the possibility of its bi-directionality. However, where I went wrong is that I ignored output impedance @ Iout. It's absolutely not "just right". It's actually very large and the current is unidirectional. In this configuration, the transduction of (V+ - V-) isn't to current- ie: Iout - but rather voltage something like Vo' = A(V+ - V-). Horowitz & Hill in the "Art of Electronics" said the output impedance of the DACAML must be high - and treated it as a voltage source output not current. They also mention the gain of this configuration to be 5000+ (early 80's text).

Using SPICE, if one input is grounded and the other input allowed to sine oscillate the output voltage Vo' is virtually a square wave under transient analysis. If the input is made small enough, the output is replicated & scaled by virtue of operating in the square's transistion region. The phenomena being manipulated in the DACAML(or it seems collector active loads) is the transistors' balancing of collector voltages(between saturation) of Q2 & Q4 to try and make up unobtainable collector current deltas resulting in a high impedance voltage gain. The modelling goes beyond using simple constant value transistor diode drops and beta.

Looking @ Leach's analysis, negative Iout(V+ - Vi) can exist (differentially - not absolutely - by superposition) wrt to the capacitor and that Qout serves as a high input impedance voltage gain. Removing the cap from the SPICE simulation still works(as you claimed) - though impacting AC performance. Again in an ac small signal sense, it's not really incorrect to view stage 1 as tranduction of V+ - Vi to current Iout - as Fredericken claims.

As a layperson - trying to learn how the basic op-amp works internally - I missed his point and took it literally in DC - but it seems to have eluded you as well.

Regards my Argumentative Jargon Laiden Lad,

Monty

+Vcc +Vcc o o | | | | 2 Ic = Bias Current Io = Bias Current | | | | | | o------o-----o | | | | |< >| o-------o----o Vo Vin(-) -| Q1 Q2 |- Vin(+) | | |\ /| Cc --- o |Ic1 Ic2 | --- | | | Vo' | |/ | o----------------------o---o-| Qout | | Iout |>

| | o | | | | | Ic1 | | o | | |/ | o----o---o-| Q4 | | | |> | | | Ic1 o | | o | | | |/ | | |--| Q3 | | |> | | | | | -------o | | | | | -Vee -Vee (created by AACircuit v1.28.4 beta 13/12/04