MIC920 input stage

Based on Fig 2.4, which shows the offset voltage going way up near the positive rail, I’d say the input stage is PNP.

Cheers

Phil Hobbs

Many thanks Phil, I have some on order and will let you know.

That's very probably right. AI gives this explanation as to why a PNP input stage is the better choice

AI Start:

The decision to use a PNP input differential stage rather than an NPN stage in a wideband, unity-gain stable op amp capable of driving unlimited capacitive loads is driven by three main architectural constraints: the requirement for a high-speed NPN voltage amplifier stage (VAS), the prevention of phase reversal during common-mode swings, and lower input parasitic capacitance.

1. Enabling a High-Speed NPN Voltage Amplifier Stage (VAS)

To process wideband signals, the internal voltage amplification stage must be as fast as possible.The NPN Advantage in the VAS: Because electrons have higher mobility than holes, NPN transistors inherently feature a much higher transition frequency (\(f_{T}\)) and lower parasitic capacitances than PNP transistors. Therefore, a high-speed op amp needs NPN transistors in its high-gain Voltage Amplifier Stage (VAS) to preserve wide bandwidth and phase margin.

Complementary Interfacing: A differential input pair must source or sink current into the next stage. A PNP input stage naturally directs its collector current downward into the base of a common-emitter NPN VAS or an NPN current mirror. If an NPN input stage were used, it would require a slower PNP VAS, bottlenecking the entire amplifier’s bandwidth.

1. Preventing Phase Reversal at the Negative Rail

When an op amp configured as a unity-gain follower drives a massive or unlimited capacitive load, the output voltage lags significantly behind the input during fast transient swings. This introduces severe common-mode stress.

The Danger of Phase Reversal: If the input signal drops sharply toward the negative supply rail (V₋) while the output is held high by a large capacitive load, the base-collector junctions of an NPN input stage can easily become forward-biased. This causes phase reversal—flipping the negative feedback to positive feedback, resulting in sustained latch-up or destructive oscillation.

The PNP Solution: A PNP input stage keeps its base-collector junctions safely reverse-biased when inputs drop toward V₋. The input stage handles large common-mode transient mismatches gracefully, ensuring the negative feedback loop remains intact even when driving "unlimited" capacitive loads.

1. Mitigating Miller Capacitance at the Input

In a unity-gain configuration, the loop gain is at its absolute maximum, making the op amp highly sensitive to any phase shift introduced by input parasitic capacitances.

Lower Collector-Base Capacitance (\(C_{\mu }\)): For a given silicon area, modern complementary bipolar processes can optimize PNP geometries specifically for low input capacitance.

Lower Transconductance (\(g_{m}\)) Stability: PNP transistors generally exhibit slightly lower transconductance (\(g_{m}\)) than NPNs at equivalent bias currents. In a unity-gain stable amplifier, a lower input-stage \(g_{m}\) pushes the dominant unity-gain crossover frequency (\(f_u = g_m / C_{comp}\)) down to a controllable region without requiring a massive, bandwidth-stifling internal compensation capacitor (\(C_{comp}\)). This leaves more phase margin to accommodate the secondary pole introduced by the external capacitive load.

END AI Summary

AI took material from TI, Analog Devices, "All About Circuits", and Youtube video by someone calling himself "Electronic Wizard" [UK and dubious], to synthesize that summary.

Yes, measurement confirmed input bias (220nA in my case) flows out of the inputs, so PNP input devices. Thanks.