Discrete JFET input stage for op-amps

Hello,

I have heard this technique mentioned before to lower the voltage and current noise of an op-amp. Can somebody point me to a schematic on how to do this? I plan to use this in a high gain current amplifier, so that means that the input will act like a virtual ground. It also has to work down to DC.

Reply to
alan
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The Tektronix 490 series of spectrum analyzers use a biopolar superbeta pair in front of a low noise op-amp in the YIG current source. mike

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Reply to
mike

Farnell list four dual N-channel FETs. Only one - the Vishay U404 - is a monlithic dual, while the others are pairs of chips mounted in a common package, which works almost as well to minimise temperature dependent off-sets.

National Semiconductor used to make a monlithic dual where the two FETs were inter-digitated, which gave very good temperature matching (though the drain-to-drain capacitance was a bit too high for good high frequency performance) but I don't know a distributor that still stocks them

The standard circuit uses a matched pair of FETs as a long-tailed pair in front of the op amp. The current through the long-tailed pair should be as high as you can make it - that means that the FET should be operating with with the gate only slightly more negative than the source, so that the gate-source diode is only just reverse biased.

The inputs to the op amp are then connected to the drains. The drain resistors have to be chosen to keep the DC voltage at the inputs to the op amp within the common mode range of the op amp, and then you have to check that the gain through the long tailed pair is high enough that voltage noise from the FETs is amplified enough to exceed the voltage noise contributed by the op amp. Too much gain from the long-tailed pair, and the extra phase shift it introduces may make the feedback loop unstable = the frequency compensation buit into the op amp is only designed to cope with its gain and phase shift - but if your amplifier is to provide a high closed loop gain, this shouldn't be a problem.

------------ Bill Sloman, Nijmegen

Reply to
bill.sloman

Take a look at the schematic of the SSM2019 on Analog Devices website - somewhat the same idea with bipolar devices for a 1nV Rt Hz opamp for audio.

Reply to
Johnson

In message , alan writes

Not sure if you are asking for this; but Linear Tech returns time and again to a discrete bog standard Philips high gm low noise fet auto biassed by a following wide band low noise voltage opamp. FET has a narrow vgs0 current range so easy to bias from a modest supply, they always show it combining nVroot Hz and attoamp input useful for diode or charge input.

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Reply to
doug dwyer

Reply to
alan

Should be possible. It is unlikely that you will be able to use low enough drain load resistors to make it worth paying for a really low voltage noise op amp like the Linear Technology LT1028 or LT1128, or the Analog Devices AD797, whose input voltage noise (around 1nV per root Hz) is about that of a 50R resistor. Even with the cheaper OP-27 -

3nV per root Hz - you will need a fairly high current FET to get the load resistors down to the 400R which generates that much Johnson noise.

The Vishay U404 I mentioned generates some 10nV per root herz with a drain current of 200uA - you'd obviously use a higher drain current, and probably a bigger FET, like the U430 or the U440 which Farnel also stocks, to get something closer to the 4nV per root herz at 10kHz quoted on the U440 data sheet for a 5mA current.

If you went for the U430 or U440, you'd need no more than a gain of two from the dual FET stage for their noise to swamp the noise generated by an OP-27 or one of its numerous equivalents - I always liked the Linear Technology LT-1007.

------------- Bill Sloman, Nijmegen

Reply to
bill.sloman

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