Second Stage of Op-Am (Current to Voltage)

the collector most likely is connected to a feed that is supplying + volts. current in the base/emitter of the transistor will govern how much pull down the + feed to the collector will get. thus the effect is you have a current that is controlling the conductance of the transistor which is pulling the + down to the ground point which then gives you a voltage shift effect. with out looking at a print that is the best i can come up with.

No. You should draw this out for us.

| |/ -| |>

| created by Andy´s ASCII-Circuit v1.22.310103 Beta

But I'm sure the 2nd stage base is maintained 1 Vbe above ground (unless you meant that the emitter goes to Vee. Maybe you mean this:

| | | | +-----+------+ | | | | |< >| -| |- |\\ /| | | | | | | | Vbe |/ Vbe +-----+ +------------| | | | |>

| | | | \\| | |/ | |---+----| | | | | | | | | | | | +------------+--------------+ created by Andy´s ASCII-Circuit v1.22.310103 Beta

current limit.

That it has two or more emitters in silicon. Also shorthand for parallel devices sometimes.

Again, how can the collector of Q6 drop below the negative supply and therefore sink current?? That node is pinned at I_Q13b*100 +

I have a question about stage 2 of a 741 op-amp - the current to voltage converter. The schematic of the 741 in following link is similar to Horowitz and Hill and Intuitive IC Op-Amps. I didn't mention I was speaking of the 741 in my first post.

Just curious what happens when I have a negative current(Iout) from the current mirror in stage 1 (between collectors Q4 & Q6) going into stage 2. I don't see how the circuit can deliver current TO the mirror except through the capacitor. I would expect the output voltage from stage 2(Q17 collector) to be constant - not an unbounded voltage ramp due to the cap for a negative Iout.

If I applied inputs w/ a very small difference in voltage in an op loop configuration, can I theoretically get a non saturated output voltage(I thought you could)? How do you compute Q17 collector voltage as a function of input current Iout or the input voltage delta?

Is the assumption that Iout = A(Vnon-inv - Vinv) where -Ibias < Iout < Ibias correct?

Regards,

Monty

In an op-amp, doesn't the differential amplifier(consisting of bias current, differential transitor pair, and current mirror)transduce the difference in input voltage to a current? From the schematic it looks as if this line, call it Iout, is the line going to the right into Q16 @ the point where Q4 & Q6's collectors connect.

I've read that this current is Iout = I_Q1e - I_Q2e where Q1 & Q2 current is conserved against a bias current. The possibility of Iout being negative is possible (-Ibias/2 < Iout < Ibias/2). Where does Iout go such that it's converted into a voltage @ Q17's collector? Or is Iout = I_Q1e - I_Q2e = A (Vnon-inv - Vinv) & (-Ibias/2 < Iout < Ibias/2) incorrect?

Regards,

M>

Yeah, the difference between the current from the mirror and the current thru Q2. You'll get a little voltage wiggle, too.

Throw that book away. It's obviously I_Q4c - I_Q6c

Doesn't exist. I told you before. That Iout node is at I_Q17 * 100 +

Where do you get that? It's vague and it doesn't even make sense. Cave men communicated better with colored stones.

It doesn't really matter at this point. It's also a voltage signal that controls Q17 which is loaded with a current source which gives a big voltage swing.

Yes. Iout is the difference between Ic2 (designated as leaving Q2-C) and Ic1 (designated as entering Q4-C). Since both are positive and about matched, their difference can take either sign.

sans stage 3 - emitter follower unity gain output.

You can think of Cc and that (nameless) rightmost transistor as an integrator (if Early voltage is infinite) or as a high-gain stage with a very low frequency pole (otherwise).

voltage Vout, that will become the output voltage of

conversion of current to voltage."

That seems to eliminate the role of that nameless transistor. Since it functions to hold its base at nearly constant voltage, by driving the top end of Cc, that is quite an omission.

calculated and how can Iout be negative? Active8, I'm

can be bi-directional.

is disagreement here from other posts.

Anybody who disagrees with the bi-directionality is mistaken.

Ok. We usually call that a current source.

In the simplest model of that circuit, you need not compute it at all. Qnameless holds it constant by virtue of it low input impedance relative to the output impedance of Q2-Q4.

Basically not sure how calculate collector voltage

currents from Q2 and Q4 make a current pump @ that

Then stop worrying about the voltage transfer function. Write the transconductance transfer function. With very little error (easily accommodated as a 2nd order effect), you can use simple device transconductance to derive it.

Not going there.

differential amplifier active load end w/ Iout(V+ - V-) =

However, Frederickson's "Intuitive IC op-amps" mentions the

choose "3) something else" because he believes that

If he truly believes or stated that, throw out his book. It will do more harm than good with respect to your understanding. Are you sure you are not mischaracterizing him?

From the schematic below, can Iout be bidirectional? Included is the schematic of Fredericken's(Intuitive IC Op Amps) basic op-amp sans stage 3 - emitter follower unity gain output. How is Iout converted to voltage?

In Frederickson's text: "The second stage of the basic op-amp converts this current back into a voltage Vout, that will become the output voltage of the op amp. An internal capacitor, Cc, is the component that does this conversion of current to voltage."

It would seem that this statement has answered my question. How is Vo calculated and how can Iout be negative? Active8, I'm speaking wrt Frederickson's text & schematic below. He clearly states Iout can be bi-directional.

First I want to make sure about the bi-directionality of Iout - it seems there is disagreement here from other posts. How would you characterize stage 1's output @ Vo'. Is it:

If it is 2, I would appreciate it if you can answer the following:

1. How do you compute Vo'? IOW, how is the transfer function of Vo'/(V+ - V-) & Vo/(V+ - V-) derived? Basically not sure how calculate collector voltage that has an active load. I've always assumed that the delta in collector currents from Q2 and Q4 make a current pump @ that point.

1. Why is the discussion about Iout = Ic2 - Ic1 relevant if 2 is true? Ga Tech/Penn State/MTU/UNLV/... lectures always have DC analysis of the differential amplifier active load end w/ Iout(V+ - V-) = Ic2 - Ic1 and stop short of stage 2 conversion of current to voltage. However, Frederickson's "Intuitive IC op-amps" mentions the cap is where the conversion takes place. Other - specifically Active8 - may choose "3) something else" because he believes that Iout can't be negative.

Regards,

Monty

| | o | | | | | Ic1 | | o | | |/ | o----o---o-| Q4 | | | |> | | | Ic1 o | | o | | | |/ | | |--| Q3 | | |> | | | | | -------o | | | | | -Vee -Vee (created by AACircuit v1.28.4 beta 13/12/04

discussion in another subthread w/ Active8 threw me

ask my real question...

wouldn't the output ramp wrt time until saturated in an

There is some input for which the output is at mid-rail. There is a small range of inputs near that point for which the limited DC gain the circuit has allows the output to not be saturated in the steady state. For any input outside that small range, the output saturates near the Vcc or Vee rail.

Approximately true. True if you ignore the limited Beta of Qnameless and assumes its base current to zero.

non zero & + or - wrt time.

Not sure what you mean here.

be operated open loop and the output is as simple as

Typically, trying to operate an op-amp open loop does not work. For most applications, it is best thought of as an integrator where the feedback drives it to a non-saturated stable operating point.

eventually - due to Iout != 0 - right?

Yes, subject to the approximation of infinite Beta.

open loop & (V+ - V-) < 0 configuration, why does

That would be where you are analyzing for finite open-loop gain. That gain is somewhat unpredictable, and can vary widely in actual op-amps.

:) All others, the schematic of op-amp stage 1 &

You can learn terminology as you go.

--

--Larry Brasfield email: donotspam_larry snipped-for-privacy@hotmail.com Above views may belong only to me.

op-amp sans stage 3 - emitter follower unity gain output.

voltage Vout, that will become the output voltage of

conversion of current to voltage."

calculated and how can Iout be negative? Active8, I'm

can be bi-directional.

there is disagreement here from other posts.

Basically not sure how calculate collector voltage

currents from Q2 and Q4 make a current pump @ that

differential amplifier active load end w/ Iout(V+ - V-)

However, Frederickson's "Intuitive IC op-amps" mentions

may choose "3) something else" because he believes

....

Well, if I was assuming that, I would have said that Ic1 and Ic2 were matched rather than "about matched".

It is obvious that either Q2 or Q4 can have the greater collector current. There's your reversal. Why should we need Spice to discern this?

If you mean to contradict with a simulation, you will have to show your circuit, its input, and the observations that you claim are at odds with my conclusions.

op-amp sans stage 3 - emitter follower unity gain output.

voltage Vout, that will become the output voltage of

conversion of current to voltage."

Cc is a feedback element in an inner loop here. In order to find where the excess phase shift of this circuit happens, it will be necessary to treat Cc as something more than just "a pole".

It is worth noting that it also serves to keep the collector-base voltages of Q1 and Q2 at about the same values. This is important for input offset stability. Your circuit without the post-diffamp gain stage will suffer a funky step response due to thermal effects that this stage will not show.

calculated and how can Iout be negative? Active8, I'm

can be bi-directional.

there is disagreement here from other posts.

Whenever Vo slews upward faster than is needed to supply Qnameless base current, it is because Iout is flowing toward the diffamp.

You seem to have ignored the additional gain that occurs thru the Q1,Q4 path. Perhaps you do not understand the role of the Q3,Q4 current mirror here. If you did, then the Iout bi-polarity would not be in controversy.

differential amplifier active load end w/ Iout(V+ - V-)

However, Frederickson's "Intuitive IC op-amps" mentions

choose "3) something else" because he believes that

What about Q4? Do you think it is in cutoff when Vo is mid-rail?

....

^^^^ That's what Monty was saying, but in his previous posts, he was refering to another drawing and here he's got the component refs all screwed around compared to that one of many of the differing 741 schems available that he linked to. At least we have a ref now.

You guys are assuming that the active load perfectly mirrors the current in diff branches aren't you?

I used to believe that the current would flow bidirectionally 'till I wondered where I'd get that reverse current. You both are welcome to simulate this circuit in Spice and try for yourselves.

I pulled out an old NPN diff stage so my circuit's upside down. Same thing.

sans stage 3 - emitter follower unity gain output.

voltage Vout, that will become the output voltage of

conversion of current to voltage."

Cc is a pole. Nothing more. I've got no Miller stage at all and I can get a voltage across a resistor which is the same thing you get if you replace the active loads with resistors.

The Miller stage bjt is for voltage gain. I'm repeating myself often here.

calculated and how can Iout be negative? Active8, I'm

can be bi-directional.

Show me.

there is disagreement here from other posts.

Show me.

Av = 40Ic_Q2(Ro_Q2 || Ro_Q4 || Ri_Qmiller) something like that. 1st order quess.

differential amplifier active load end w/ Iout(V+ - V-) =

However, Frederickson's "Intuitive IC op-amps" mentions the

choose "3) something else" because he believes that

Because there's nowhere to get it from!

I didn't write the POS.

Told you what you wanted to hear. You need to hang with Paul Burridge.

ROFLMAO

So, you believe that Q4 cannot conduct at a lower Vce than that? How do you think saturated BJT's work?

You can get it with the circuit as Monty drew it. I see no contradiction here beyond bare assertion.

op-amp sans stage 3 - emitter follower unity gain

voltage Vout, that will become the output voltage

conversion of current to voltage."

If the Qnameless/Cc combo provided only a single pole, calling "a pole, nothing more" would be fine, I guess. My point is simply that it has more effect in applications where closed loop stability becomes an issue.

Consider this point carefully when asserting that I was unable to discern the DC operating point.

calculated and how can Iout be negative? Active8, I'm

Iout can be bi-directional.

there is disagreement here from other posts.

I do and did see it. It is a minor term.

You would not be able to state such a non-fact if you had understood my point about thermal response. To get there, I had to know the approximate DC biasing.

differential amplifier active load end w/ Iout(V+ -

However, Frederickson's "Intuitive IC op-amps" mentions

may choose "3) something else" because he believes

In that state, Q2 and Q4 collector currents are nearling balanced. To say the output comes from one only is oversimplified. Once at that state, if Vo begins to move positive at a rate faster than Ib(Qnameless)/Cc, net current at Vo' will be leaving to the left. According to your way of thinking, it would be going to Q4.

Monty Hall wrote: (snip)

(snip)

I haven't been following the details of this thread very well, so I hope this is useful. Have you read through the National semiconductor opamp tutorial, yet?

It goes through a generic but simplified opamp, pretty thoroughly.

Because you were blabbering about Q1, Ic1, with no circuit to refer to. Notice I correctly guessed the circuit, not the reference designators.

They're not, but they don't get really wierd 'til you push the rails.

I told you Iout can't be negative before I pulled that circuit. Don't be an ass. You'd probably save time and frustration if you

I told you. The circuit can never do this. Vo' is pinned at 1 Vbe above Vee. If you drove Vin(+) so high that it cuts off, Q4 will try to get that current from the next stage and it can't. Q4's collector will drop below the Vbe (head for the lower rail) of the 2nd stage and the 2nd stage will be in cutoff as a result. Replace the 2nd stage with a resistor connected to (Vcc - Vee)/2 or if you want that bidirectional behavior.

Was that articulate enough?

I don't have it and I suspect he's *not* talking about the same 741 circuit. If he is, he can't see.

I didn't. I first explained to Monty that you can't get a reversal of current in this circuit no matter how hard you try - you can't get a voltage at that Iout node that's lower than the voltage of the Miller stage emitter. There's no source.

Which were wrong. Load the diff stage with a resistor connected to halfway between the rails and you *can* get that current reversal.

op-amp sans stage 3 - emitter follower unity gain output.

voltage Vout, that will become the output voltage of

conversion of current to voltage."

WTF? Poles and zeros are *exctly* what you want to look at when determining phase shifts.

calculated and how can Iout be negative? Active8, I'm

can be bi-directional.

there is disagreement here from other posts.

That's an effect of Cc. Iout would never need to *draw* current in order to *supply* it. OP is talking about the diffamp demanding a current reversal and that can't happen in this circuit.

You can not find any DC state in the circuit below where Iout reverses. Post the voltages where it happens.

I just love the way you guys are talking poles and integrators when you haven't even established the DC bias point.

No I haven't. See the Q4 impedance term in || with the other loads?

You can't even seem to determine zero input bias point voltages it all one needs to do to show that bidirectionality can't occur here.

differential amplifier active load end w/ Iout(V+ - V-)

However, Frederickson's "Intuitive IC op-amps" mentions

choose "3) something else" because he believes that

ROFLMAO. When Vo is mid-rail, currnt flows to the right from the Vo' node. So even if Q4 was in cutoff (and it isn't), it wouldn't matter. The current would come from Q2.

Top posted. In a DC analysis, the capacitor has no function, you could look at it as sinking or sourcing current in a transient analiysis, or in AC it is simply miller effect throwing in a low frequency pole, as you said. This guarantees stability at a gain of one, without external compensation. The mirror never pulls current out of the base of the second stage, it just steals the base drive, supplied by the trasistor in the diff amp, above, depending on how the input amp is tipped. Can't read your diagram.

It says I don't have permission to access the link posted.

Looking at it open loop is meaningless in the practical sense, it could theoretically balance the output, but the Gain A is probably

There should be a pullup >I'm reading Tom Frederickson's "Intuitive IC Op Amps" - in particular pg 15

Let's see ... You have Ro_Q4 in parallel with Ri_Qmiller. Ri_Qmiller is going to be in the neighborhood of Beta * (Vt / Io) whereas ro_Q4 will be something like Vearly / Ic1 So, for Ri_Qmiller to be comparable to Ro_Q4, (and taking Io to be similar to Ic1, an assumption generous to you), we need to have Beta * Vt =~ Vearly or Beta =~ Vearly / Vt. Typical values of Vearly are 40, and Vt is about 26 mV, so you need Beta near 1500 in order to keep the Q4 impedance term from becoming minor. It gets worse with a more reasonable assumption about Io relative to Ic1.

Perhaps you have overlooked the fact that the smaller impedances dominate in a parallel connection.

Do you believe that Ic1 can never exceed Ic2? If so, what do you suppose happens if (Vin(+) - Vin(-)) is more positive than, say, a few 10's of mV? If not, why can't you see that since Iout is defined as Ic2-Ic1, that expression can become negative? And please, no jabber about the steady state. We are adressing your proposition, and I quote: "I told you Iout can't be negative" and "I used to believe that the current would flow bidirectionally".

This is getting a bit wearying, so I may not respond further.

Top post

Multiple emitters is common practice. Virtually all TTL inputs are done that way. In an epitaxial process, One simply diffuses 1 to n emitters into the base region, of the NPN input transistor, and connect them to the outside world. The active input state, per emitter is is low.

Dan