Miller effect in CMOS inverter!

Miller capacitance effect is normally meant to be the effect of multiplication of the feedback capacitance on the input current during output swing.

Since you are assuming that the input voltage on the first stage is independent of the input current, there is no miller effect in the first stage. You still have to account for the feedback capacitance effect on the output rate of change, since it still has to be charged through the output impedance after it is reverse charged by the fast input swing.

While that is happening, the second stage miller effect adds current load (to that charging the first stage output to supply capacitance and second stage input to supply capacitance) on the first output. The current through the feedback capacitance also loads the second output (in addition to that charging the second output to supply capacitance.

To better show the situation:

At page 4 it speak about the miller effect, it explain that there is a complete swing in the input voltage and a complete swing in the output voltage, and so the multiplication of the Cgd!

I'm studing an exercise that it ask to calculate the propagation time of two inverter in cascade!

The solution speaks about the Miller effect across the Cgd (gate-drai acapacitance) of the first inverter's PMOS and NMOS.

But I ask, why take into consideration the Miller effect as a 2 factor moltiplication of Cgd i the voltage at the drain terminal don't have a complete swing? It can be because the swing in the circuit is however complete even if we consider the first 50% of the swing?

If it's true, there's another problem!

Analysing the second inverter,the exercise solution show,there isn't Miller effect because of the second inverter commutation don't come before the last stage vout goes under VDD/2!

This confuse my already very confued ideas about the problem!

If someone want help me to understand...

Thanks in advance and still sorry for my very bad english