MOSFET: why is it called Miller plateau?

Miller Effect is now a loose description of the effective multiplication of plate-grid or drain-gate capacitance by the negative voltage gain of the device. In the active gain region, it makes sense.

In a switching mosfet, the concept aligns with how much gate charge it takes to switch. It's just delta-q = c * delta-v. Gain makes delta-v big.

We call that Miller Effect and Miller Capacitance as a sort of shorthand. Language purists often disapprove of the ways that engineers talk to one another. Let them freeze in the dark.

It indeed does make sense, but not in quasi-static conditions. A capacitor has no useful DC impedance.

This is not about purism, but about my own consistency check of the understanding of the Miller effect. I am perfectly fine with you calling that region "Miller plateau" or "Einstein-Podolsky-Rosen plateau" -- it has exactly nothing in common with either of them, so both are equally OK. Miller wins for being shorter.

Best regards, Piotr

The equation, Q = C V works at DC. Whenever you want to change the voltage on a capacitance, you must keep track of charge. In fact, for convenience, MOSFET Miller plots are usually made virtually at DC. In x-Chapters, 3x.12, there's a nice bench test circuit, typically run with 1mA gate current, that we use to make some fascinating gate-charge measurements, as a function of the drain supply voltage. Some MOSFETs have a "textbook" flat curve, others slope upwards.

The plateau exists while Vd is changing. It's Cgd that takes all the charge, not Cgs. In my mind, the Miller effect describes exactly that. Is the plateau still there if you keep Vd constant?

Jeroen Belleman

We don't think of a cap as having a DC impedance. That's meaningless. But it still has capacitance even when there's no voltage across it.

Right, in casual speech, it can refer to Cdg, or Cdg*gain, or the charge equivalents. "The Miller capacitor" sometimes means any capacitance between drain and gate. Speech can be casual, but when it gets down to numbers, it has to be more precise. Doing the numbers makes the words not matter much.

We say things like "zero" and "infinite" to mean small and big, and that works too.

Piotr Wyderski wrote in news:qsojhq$1vrh$ snipped-for-privacy@gioia.aioe.org:

Because it established a ceiling for the miller region, a plotted graph which describes the turn on event of the UUT. It has a start point and an event duration, and the miller region and miller plateau lie within that.

Taking readings on several aspects notes one such reading which once switching begins, rides flat until the switch on event is complete. The ON resistance takes 'a moment' to propagate through the entire gate. It is fast but not instantaneous. That is why they end up classed by how fast they can switch for the radio boys. For power it is how 'hard' they can switch and how fast, and that event takes a bit. It does not slew up instantly. (or down for the resistance).

Below is the setup I have in mind. You can see the plateau, but the Cgd impedance is huge at this time scale. My working hypothesis is that this is a purely geometric effect of the conducting, quasi-metallic channel formation and the corresponding growth of the gate-channel capacitance. Since the channel is effectively connected to the source, this implies growing Cgs and hence flat Vgs curve (up to the channel saturation point). This also explains the Cgs(Vds) dependence. This is a kind of phase transition, not a Miller issue. Where am I wrong?

Best regards, Piotr

Version 4 SHEET 1 880 680 WIRE 480 -192 368 -192 WIRE 368 -160 368 -192 WIRE 480 -160 480 -192 WIRE 480 -64 480 -80 WIRE 368 -48 368 -80 WIRE 192 32 144 32 WIRE 304 32 304 -16 WIRE 304 32 272 32 WIRE 320 32 304 32 WIRE 144 80 144 32 WIRE 368 80 368 48 WIRE 144 176 144 160 FLAG 144 176 0 FLAG 368 80 0 FLAG 480 -64 0 FLAG 304 -16 Vgs SYMBOL voltage 144 64 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V1 SYMATTR Value 10 SYMBOL res 288 16 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R1 SYMATTR Value 1Meg SYMBOL nmos 320 -48 R0 SYMATTR InstName M1 SYMATTR Value IRFP2907 SYMBOL res 352 -176 R0 SYMATTR InstName R2 SYMATTR Value 1 SYMBOL voltage 480 -176 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V2 SYMATTR Value 10V TEXT 110 200 Left 2 !.tran 100m TEXT 112 232 Left 2 !.IC V(Vgs)=0

What impedance are you defining? I don't see an impedance statement on the sheet.

There's nothing quasi-stable about this system, the drain voltage is changing rapidly (it's also not a simple linear ramp, if you want to think of that as a quasi-stable condition).

There's nothing physicsy about it: the same gross behavior can be demonstrated with a pure SPICE ideal amplifier with finite gain and saturating output.

The Miller theorem shows that we can express Cdg as an effective Cgs, but it's only a reflection of the change in drain voltage, and as soon as that change goes away, the Cgs(eff) goes away. Try clamping drain voltage with a diode from another voltage source. :)

Nothing discontinuous occurs, nor anything chaotic or difficult (impossible?) to model; it's not a phase transformation, at least not a low order one.

Tim

The plateau vanishes when you keep Vds constant. (SPICE models don't smoke.) However, Vg does not exactly fit an RC rise, so the effect you mention, or something like it, does indeed come into play and is modelled.

There is some talk of non-linear depletion layer capacitances in the description of the model in the LTspice docs and there are 14 references to seven different MOSFET models. I think I'll call it a day.

Jeroen Belleman

I wonder why engineers have a problem communicating with other folks?

If you mostly communicate with other engineers you tend to take rational behaviour as the norm.

Inanimate chunks of metal and silicon are unresponsive to spin.

Bill Sloman wrote in news: snipped-for-privacy@googlegroups.com:

The quantum dot boys would disagree.

Different kind of spin. Theirs is quantised, and happen in the real world (though a fairly inaccessible part of it).

If you reduce the drain resistor, to prevent drain voltage change, the plateau disappears.

RL

snip

Right; as the drain voltage rises, Cdg gets charged up by drawing current from the gate driver. Any impedance in that path affects the gate voltage.

Clifford Heath

Rick C wrote in news: snipped-for-privacy@googlegroups.com:

Because engineers are scientists, and most other folks are superstitous, misled dopey dipshits.

There are exceptions. Some of the engineers slovenly grasp and try to retain their dopeyness and others instill it deeply through self imposition.

Makes folks like Rod Serling write human social stories about it.

Well, we could all agree to call it Wyderski-Plateau :-)

Joerg wrote in news: snipped-for-privacy@mid.individual.net:

That's just too wyrd.

A boy needs a beer after hiking up that high. Miller High Life is drinkable on a hot day.