Data Decoding at 10 Gbit/s

Dec 21, 2005 2 Replies
W

Hi, Xilinx have filed for 22 patents to implement 8B/10B algorithm.

IBM filed the 8B/10B original patent in 1981. Now 8B/10B algorithms are so popular that all SERDES specifications use the 8B/10B like what ASCII is to computer industry.

Most of 22 Xilinx 8B/10B patents are pending. You may print out what have been approved as a patent. Their experiences will certainly help you do understand how to design a 8B/10B circuit.

Sorry, all those circuits are still pending. One that is approved is a software flow map.

Weng

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M

Hi,



I would like to design a 16 channel SERDES ASIC in 0.13µm running at 10 Gbit/s per channel. For transmission a standard 8B/10B is to be applied. My concern is now how to achieve real-time decoding of the 8B/10B transmission code at 10 Gbit/s with that technology? Can that easily be achieved? What is state-of-the-art? As far as I know the 8B/10B decoding cannot be down by a simple lookup table because the corresponding code words depend on the running disparity of the previous transmitted data and there is no simple



1-on-1 mapping. Since the 8B/10B coding is a self-synchronizing (?) code (i.e. the clock can be retrieved from the transmitted data) I would have to use a kind of clock recovery at my SERDES input. Another question would be if a PLL at the input is advisable or even feasible at data rates of 10 Gbit/s.

I would be very thankful if some of you could give me a hint.



Best Regards



Martin


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K

Vitesse is certainly achieving >10Gbit/s in 0.13um - ISTR that they also have done 12.5Gbit/s. They have chips doing 10Gbit/s SERDES for at least 2 years now, but as far as I remember, this is only 1-4 channels per chip. YMMV.

It's only a 1GHz encoding/decoding rate (parallel datarate), so I don't see why it should be a problem. Again, Some/all of Vitesse

10Gbit/s chips implement 8B/10B.

Disclaimer: I don't work Vitesse (any more).

Kai

Kai Harrekilde-Petersen
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