If my phase detector for PLL is D-flipflop with Reset, what what the output be when the input B is lagging input A (reference) by 180 to 360 degrees?
Assume the inputs have same on time (e.g. 5ns) and same period (e.g.
Thanks, Vitaliy
On 5 Mar 2006 11:15:04 -0800 in sci.electronics.basics, snipped-for-privacy@ee.ryerson.ca wrote,
Do not post copies of your question in multiple newsgroups. Pick one.
i think it should be no pulse output and if its designed like think it is ? you will only get a pulse output when one freq is just behind the other! other wise no pulse at all! this makes sure that correction is performed only in one direction. this is the same logic used when taking the A and B output from an incremental encoder to detect direction of rotation!, one way will generate a pulse and the other direction will generation no pulses. the pulse that is generated is the time width of when A and B happen to be one at the same time which is usually 25% duty cycle . in the case of PLL's this duty cycle varies depending on how far out of lock it is.
You might be talking about frequency detector, which might be different. Here is my lab manual (labs 3 and 4).
Vitaliy
Have something to add? Share your thoughts — no account required.
Ask the community — no account required