Verifying Chip Capacitors

response

hard to

I remember seeing the Clark boards for a late-model bipolar mainframe, a

3090ES or something like that, circa 1990. One of the power supply busses was +3.3V at 9000 amps. It was a heavy solid copper angle, about 2 inch by 2 inch by 1/4 inch.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs 
Principal Consultant 
ElectroOptical Innovations LLC 
Optics, Electro-optics, Photonics, Analog Electronics 

160 North State Road #203 
Briarcliff Manor NY 10510 USA 
+1 845 480 2058 

hobbs at electrooptical dot net 
http://electrooptical.net

worth

Sure. We typically have anywhere from 4 to 12 power rails. Like +0.9, +1.2,

+2.5, +3.3, +5, +5A, -5A, +12, and a couple of VREF type things. Sometimes more, like +-48 or whatever, or +1.1 for some PHY type thing.

Right. Why pay for courses and do a lot of engineering when power supplies are easy and almost always work?

The mixing of caps with various SRFs is mostly done based on authority and hearsay. Sure it works. And it works just as well if you don't do it.

Maybe you're talking about science. Engineering is doing what works efficiently. I don't do extensive analysis - thermal, magnetic, mechanical, nuclear - when I don't need to.

It's not always bad, but it's not

That's what engineering is. You don't do full Maxwells Equations and first-principles quantum physics when you design a simple opamp circuit. Neither do I. But we don't "push stuff around." We draw schematics, lay out boards, and have people assemble them for us. No prototypes, not much simulation. Over 95% of the time, it works on the first try.

I

ESL+ESR,

pretty

the

Normal stuff, mixed-signal systems, uPs and FPGAs and ADCs and opamps and things. Lots of picosecond timing and low-level signal conditioning. I've posted lots of pics of my PC boards.

At what frequency does the impedance

I work in time domain, not frequency. I TDR a plane and see its current-step response. It looks like, say, a 1500 pF cap without much personality, just some very fuzzy hints of edge/corner reflections. Add some bypass caps, and it looks like a bigger cap, and the reflection hints go away. It's not a big deal.

So far, everything works. Engineering hours are better spent on things that add value.

oscillations,

dynamics

If they use 400 caps, when 20 would do, that's not good engineering.

The only bypassing problems that I sometimes see are low frequency stuff, microseconds to milliseconds. That deserves attention. When you see a lot of jitter in a fast circuit, look first for *low* frequency power supply noise.

--

John Larkin                  Highland Technology Inc 
www.highlandtechnology.com   jlarkin at highlandtechnology dot com    

Precision electronic instrumentation 
Picosecond-resolution Digital Delay and Pulse generators 
Custom timing and laser controllers 
Photonics and fiberoptic TTL data links 
VME  analog, thermocouple, LVDT, synchro, tachometer 
Multichannel arbitrary waveform generators

planes,

much of

supply

periodically gate

current

250 MHz,

any

low-frequency response

config

actual

to

convenient coax

It's hard to

(transient +

drawing

to

Indeed, browsing some AMD chips, peaks of near 75 A at 1.4 volts are normal, averages are a bit lower due to package continuous dissipation being 110 W or less. 32 nm SOI process.

?-)

22,000 data points. Yours? Averages apparently.

Lots of zeros in that data too. I replaced that with cut and pastes of existing data for the purpose of making the plot.

I have one that handles leap years too.

Not very 'purty' at all. Mine is, however.

Almost 28K lines so far. Spot temperature measurements, not averages.

I had to extend the plot y-axis to -10F. We had a cold front move though. The official low temp in Truckee, at the airport in Martis Valley, was -22F, but that station is out in the open, always higher/lower than realistic temps in the woods.

I don't see any zeroes.

I am *not* going to execute a spreadsheet posted by some Chairman Meow who has threatened me numerous times and who won't reveal his actual name.

The gnuplot thing works great.

--

John Larkin                  Highland Technology Inc 
www.highlandtechnology.com   jlarkin at highlandtechnology dot com    

Precision electronic instrumentation 
Picosecond-resolution Digital Delay and Pulse generators 
Custom timing and laser controllers 
Photonics and fiberoptic TTL data links 
VME  analog, thermocouple, LVDT, synchro, tachometer 
Multichannel arbitrary waveform generators

It's 'fun' trying to explain to some so called techs why the CPU power supply is right next to the CPU, and that there are valid reasons to put the low ESR caps so close to the CPU.

CPUs are special in that they can go from low current to scores of amps in nanoseconds, as some process wakes up. FPGA designs seldom do that... they mostly just tick along, clocking all of their flops all the time.

--

John Larkin                  Highland Technology Inc 
www.highlandtechnology.com   jlarkin at highlandtechnology dot com    

Precision electronic instrumentation 
Picosecond-resolution Digital Delay and Pulse generators 
Custom timing and laser controllers 
Photonics and fiberoptic TTL data links 
VME  analog, thermocouple, LVDT, synchro, tachometer 
Multichannel arbitrary waveform generators

MHz,

response

config

coax

hard to

ISTR, mainframes used either +1.25V and -3.0V (ECL, or "CSEF") or ground, -1.5, and -3V (TTL). There weren't many TTL models (only one of the 3080s, IIRC). 9kA seems high but not tremendously so (the CPU was 9 TCMs at 1.5KW).

MHz,

response

config

coax

hard to

Could have been -3V. I remember it was about 27 kW, which would be about right.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs 
Principal Consultant 
ElectroOptical Innovations LLC 
Optics, Electro-optics, Photonics, Analog Electronics 

160 North State Road #203 
Briarcliff Manor NY 10510 

hobbs at electrooptical dot net 
http://electrooptical.net

current

MHz,

response

config

coax

hard to

Do you remember the system or approximate year? Just trying to refresh my memory, too.

The spaces both before and after your date field entries is LAME formatting.

It requires additional handling after the import operation.

Pretty lame. Making a proper CSV file is about as academic as hooking up a printer cable.

Either your data logger or *your* programming of your data logger output is adding these spaces, and they are NOT needed. a CSV will fill field values and you do not need to space anything off for it.

But it works.

Excel is lame. Gnuplot is smart enough to parse it.

The entire gnuplot control script is

cd "c:/_Truckee" set pointsize .25 set datafile separator "," set xdata time set xlabel "Date, time" set xlabel offset 0,-1 set yrange [-10:100] set xtics format "%m-%d %H" set xtics rotate by -30 offset -1 set mytics set grid xtics ytics mytics set timefmt "%m-%d-%Y , %H:%M:%S" set terminal pdfcairo size 9,6.5 set output "Tplot.pdf" plot "log.csv" u 4:1 t "Inside", "" u 4:2 t "Outside",\ "" u 4:3 t "Boots" unset output

It's not a "data logger", it's a PowerBasic program running on a mini-ITX PC, Windows XP, appending one line a minute to a CSV file shared by Dropbox. Works fine.

--

John Larkin         Highland Technology, Inc 

jlarkin at highlandtechnology dot com 
http://www.highlandtechnology.com 

Precision electronic instrumentation 
Picosecond-resolution Digital Delay and Pulse generators 
Custom laser drivers and controllers 
Photonics and fiberoptic TTL data links 
VME thermocouple, LVDT, synchro   acquisition and simulation

Geeze! 9000 Amps!!! That's a hell of a machine. I thought I worked on a city dimmer, powered by 220V and internally running big braided cables for DC power distribution. Lots of ECL gate arrays. But I guess that is still in the minor leagues compared to this.

It was a fast machine though. Around 1985 and it did 100 MFLOPS. I think it was the fastest machine at the time other than a Cray, which of course, it didn't really come close to, but it was well under a mil. I think the base price was about $200k. These days a cell phone does that in fixed point.

Rick

No... John... YOU are lame.

You are, in fact, as lame as a person claiming to be a man can get. This "excel is lame' crack proves that fact.

excel can also parse it.

The problem is your retarded decision to add the space to begin with.

The only element in the whole thing NOT smart enough is you.

more,

This isn't going anywhere. It is clear that you don't really understand PDS design and have done lots of stuff where you can get away with typical designs.

I'm not talking about power supplies. I'm talking about the PDS, power distribution system. "almost"? That's what I'm talking about.

I've already quoted Lee Ritchey. I took his course where he shows the theory, simulation results and then the board that he built to test it. That's not "hearsay".

efficiently.

I

Yes, your designs have not needed significant engineering in the PDS. That's not true for all designs and may not be true for yours in the future.

Neither

and

You can diss the idea all you want, but it is important to know how to apply proper engineering when it is needed. I don't consider 95% to be very good really. Startup companies have folded because of design failures like this.

What I

ESL+ESR,

pretty

the

posted

That's not a PDS requirement. In other words, you haven't built anything that needed rigorous analysis of the PDS.

some

looks

I didn't ask about the PDS, I asked about the noise the chips produce.

add

You keep saying things like 95%, "almost" and "so far". That's not engineering.

Now you are talking nonsense. Your method of adding single value caps until you can get the board to work is the one that uses lots more caps to get the same board impedance across the spectrum.

Ok, if you can get your boards to work this way, that's fine. I agree that most designs don't need so much attention to the PDS. I'm just saying that the idea that some designs need to be done well and properly is not "superstition". Let me know when you design something transmitting or receiving 10+ Gbps without giving the *full* design a proper noise analysis.

Rick

dissipation

in

they

In both cases it is a combination of design and workload dependencies. Just the same most FPGA designs are a lot less sensitive to workload.

?-)

Excel is for people who never learned to program.

--

John Larkin Highland Technology Inc

jlarkin at highlandtechnology dot com

Precision electronic instrumentation Picosecond-resolution Digital Delay and Pulse generators Custom timing and laser controllers Photonics and fiberoptic TTL data links VME analog, thermocouple, LVDT, synchro, tachometer Multichannel arbitrary waveform generators

though. The

but

temps in the

of

who has

Should anybody give a flying donut at a rolling leap, mediafire has a preview feature that will give a look at what the result might look like without the file ever being transferred to your computer. I used it and joke sheppard's file ain't nearly as 'purty' as your plots. Three separate graphs, can't 'e get XL to do multiple lines on one chart? And far less timespan, just junk by comparison.

?-)

As John mentioned, all flops in an FPGA get clocked simultaneously. Even clock gating doesn't drop much power because the entire clock tree is still hot. FPGAs don't use much in the way of dynamic power management, or really, power management of any kind. These are all "tricks" that CPUs have used for decades that really aren't applicable to FPGAs.