Verifying Chip Capacitors

distribution of various decoupling cap values.

"Black

I build picosecond stuff that works. Do you?

I often include SMA connectors on PCB layouts, so I can TDR/TDT the power planes on bare boards and measure the plane noise on operating boards.

A plane/pour system is a good HF cap all by itself. Adding a few more ceramic bypasses here and there makes it better. It's pretty much that simple. Of course, if you expect gross low-frequency current steps, you need enough bulk capacitance to handle that until the power supply can respond.

Most systems are grossly over-bypassed. And the classic "use lots of different value caps" papers were mostly authored by people who sell caps.

I do mixed-signal stuff, uPs and FPGAs and fast ADCs and picosecond delay generators. I don't use a lot of caps and I've never used too few.

Here's a signal conditioner and a 250 MHz 12-bit ADC inches away from a big FPGA and a bunch of switching power supplies and line drivers. It has a few 330 nF bypass caps here and there. It worked first time. There are no parts on the bottom side.

Absolutely!

One piece of bad info is that all systems need to be treated

Another is that high speed systems need a lot of different bypass caps. On a multilayer board, bypassing is easy.

But assuming that the info on how to design the PDS for

HoJo's Black Magic book *is* silly.

--

John Larkin                  Highland Technology Inc 
www.highlandtechnology.com   jlarkin at highlandtechnology dot com    

Precision electronic instrumentation 
Picosecond-resolution Digital Delay and Pulse generators 
Custom timing and laser controllers 
Photonics and fiberoptic TTL data links 
VME  analog, thermocouple, LVDT, synchro, tachometer 
Multichannel arbitrary waveform generators

Oh dear Mr Nymbecile. You don't get any better.

Perhaps one of your new year resolutions should have been to try and keep your favourite fetish to yourself.

No, I only point out your scat fetish, which we can see is still in overdrive.

Besides, Speff is a nice person, and you're not.

--

John Larkin                  Highland Technology Inc 
www.highlandtechnology.com   jlarkin at highlandtechnology dot com    

Precision electronic instrumentation 
Picosecond-resolution Digital Delay and Pulse generators 
Custom timing and laser controllers 
Photonics and fiberoptic TTL data links 
VME  analog, thermocouple, LVDT, synchro, tachometer 
Multichannel arbitrary waveform generators

A claim which is untrue, you RETARDED FUCK!

You have made more references in the last year than I... Oooops!

You made no reply to the spreadsheet I spent my personal time on preparing for you. You were too busy latching onto the open source solution you were given, and decided to simply ignore me and my contribution.

You are a real prize. and you cannot figure out why you get referred to as the most filthy media the earth produces. and then it comes out of the orifice you claim is civil as well.

How quaint... No... how utterly vile of you.

I couldn't see that it did anything useful. But thanks for trying.

The gnuplot thing works great. I double-click on a batch file, and the pdf appears in a couple of seconds. The x-axis scaling is adaptive to the number of points in the file, something that is apparently difficult to do in Excel.

Purty, huh?

--

John Larkin                  Highland Technology Inc 
www.highlandtechnology.com   jlarkin at highlandtechnology dot com    

Precision electronic instrumentation 
Picosecond-resolution Digital Delay and Pulse generators 
Custom timing and laser controllers 
Photonics and fiberoptic TTL data links 
VME  analog, thermocouple, LVDT, synchro, tachometer 
Multichannel arbitrary waveform generators

It did what you asked for.

You said your data points were limited.

It plotted your entire set.

I updated it too.

You failed to put a header in naming what the data fields were so I guessed at them.

That is not very many data points at all. Not at all what you asked for in your post.

Mine seems to be more fuzzy as the number of points gets larger.

It would seem that what you need is a "selection Window' where you pick a specific week, and all entries for that week show up in the plot, based on which week you selected.

Of Course, data for that week (or whatever time segment) would have to be a full set of readings. Or the plot will screw up on looking up the data.

I think I can do it. I think I already have a blood pressure log that does a similar function which I can look back on ad use pieces of.

You just paste in new data sets occasionally, which can also be automated. But you have to accept a macro rich VB spreadsheet at that point.

sea of decoupling chip capacitors, many of which are too small (e.g., 0402) to have markings that would reveal the capacitance value. Other than infer ring that they are mostly correct because the board works or removing them and measuring their value, do any of you have some procedure to verify that the right capacitors have been used.

e

ribution of various decoupling cap values.

Thanks for your input, Phil. Though I agree that in many cases the low impe dance of the plane reduces dependence on a careful distribution of high and low freq caps, my concern was simply how one can verify that the decouplin g caps on the board match the schematic.

Darol Klawetter

coupling capacitor of each value and measure them. If they are correct, the n we can have high confidence that all caps of these values are correctly p opulated because the pick and place machine must have been loaded correctly for our small sampling to be correct. This would be costly for high volume production but could be worthwhile during prototype checkout.

Ahh, yes. One could have board-resident representatives each capacitor type , and it wouldn't, at least in my case, require much board area. Assuming P &P assembly, and a board functioning at full speed, one could have high con fidence that the decoupling scheme matches the design.

distribution of various decoupling cap values.

"Black

That is exactly the sort of stuff that makes you sound like a hack. "I use the XYZ rule of bypassing and all my boards work". Yeah, but what does that prove? Mostly it means using way more caps than needed.

planes

I won't argue about the "over-bypassed" boards. But if you use the methods that are promoted by the rational engineers who *don't* sell caps, you can actually use a lot fewer bypass caps than if you just use one value.

FPGA

That's not bad info, it is useful if you actually engineer your PDS. Or you can just scatter around a few caps and hope it works like the others you have done seem to.

I have never studied "HoJo's" book. I took a class with Lee Ritchey and was very impressed with his knowledge, but more importantly his techniques of understanding the theory, analyzing it in simulation, and then proving it all correct by building the hardware. He showed that caps on good ground/power planes don't need to be as close as possible to the pins of the chips, again, by using all three methods.

Rick

distribution of various decoupling cap values.

"Black

Me? Use more caps than needed? I use less than a tenth of the number of caps that Xilinx recommends... average maybe three per voltage per FPGA. Hmmm, maybe that is too many.

People have all sorts of beliefs about bypassing, and the beliefs are fervently held because they work. Fact is, on a multilayer board, just about any bypassing scheme works. I know a guy who doesn't use bypass caps at all, and his stuff works.

I saw one big Advantest board being stuffed by a gatling gun chip shooter. It had about 3000 bypass caps. I bet it worked too.

planes

different

I use 330 nF because they are cheap and we have lots of them. Why would I mix them with any smaller value? For a given package, ESL is independent of C, and HF impedance is dominated by ESL. More C is better for low-frequency current steps, so use the biggest value that's still cheap.

FPGA

Good. Don't.

I took a class with Lee Ritchey and

As I said, just scatter a few 330n bypasses here and there on the planes. I figured that out in about a half hour of TDR testing.

--

John Larkin         Highland Technology, Inc 

jlarkin at highlandtechnology dot com 
http://www.highlandtechnology.com 

Precision electronic instrumentation 
Picosecond-resolution Digital Delay and Pulse generators 
Custom laser drivers and controllers 
Photonics and fiberoptic TTL data links 
VME thermocouple, LVDT, synchro   acquisition and simulation

That is not the same data set.

Send me that csv.

of

No, it changes - gets one new line of CSV data - every minute. That's probably excessive... I might change it to one line every 2 or 4 minutes, and eventually edit out the older stuff. It's up to almost a megabyte now. Dropbox only distributes changes, so all my linked computers get updated without a lot of web traffic.

Dropbox is a whole new perspective on realtime data logging and remote control.

You should be able to read it live here

The gnuplot thing is working great, so don't go to a lot of trouble doing Excel macros for me.

Hey, a cold front just swept through, and the heat kicked on for the first time in over a week. Fresh snow!

Same link as above, but updated file. I could write a batch file that would kick off gnuplot to regenerate that PDF file automatically every hour or whatever. Microsoft for some bizarre reason deleted SLEEP from their XP batch file vocabulary - it just hangs now - but I wrote a little replacement.

--

John Larkin                  Highland Technology Inc 
www.highlandtechnology.com   jlarkin at highlandtechnology dot com    

Precision electronic instrumentation 
Picosecond-resolution Digital Delay and Pulse generators 
Custom timing and laser controllers 
Photonics and fiberoptic TTL data links 
VME  analog, thermocouple, LVDT, synchro, tachometer 
Multichannel arbitrary waveform generators

distribution of various decoupling cap values.

most

"Black

But it always does. And I can't save a few bucks when I'm using 20 cents worth of bypass caps on a whole board.

different

Superstition. All my boards work with very few caps.

TDR is time domain, so I didn't measure z-vs-f. TDR shows step response. What I observed is that a power:ground plane pair looks like a very good, low ESL+ESR, fairly low-Q capacitor. Or you can think of it as a very low impedance, pretty lossy sheet transmission line. As you add bypass caps pretty much anywhere, the impedance goes down.

That's about it.

Has anyone here done a multilayer board, with power and ground planes, where your bypassing scheme *didn't* work?

I have had some low frequency problems, mostly slow bounces or LDO oscillations, but they weren't high-frequency bypassing issues, more regulator loop dynamics things.

--

John Larkin                  Highland Technology Inc 
www.highlandtechnology.com   jlarkin at highlandtechnology dot com    

Precision electronic instrumentation 
Picosecond-resolution Digital Delay and Pulse generators 
Custom timing and laser controllers 
Photonics and fiberoptic TTL data links 
VME  analog, thermocouple, LVDT, synchro, tachometer 
Multichannel arbitrary waveform generators

I haven't but a cow-orker has. I fixed it with a few (8, IIRC) caps. His next board spin had a cap everywhere there was space to put two leads .100" apart (radial caps, before SMT).

oscillations,

This was a problem with dI/dt on the power planes. TTL and really ugly spikes everywhere. The edge-triggered TTL clocks really didn't like it at all.

That said, I'm sure I'm guilty of using far too many caps. It's a lot easier to rationalize in a design review than "too" few. I'm doing prototype or "platform" work now, so cost really isn't an issue, though. A few bucks is cheap insurance. When they go to make a million, it's a different story but it's not my design anymore.

OTOH, our prototype contract assembly house forgot a bunch on the DSPs on the first spin of one of my boards. I only noticed it because I got the PLL on the wrong voltage and was looking for a place to attach a wire.

I've never had a bypassing failure when I've used planes.

I have an FPGA design I call "Chip Heater" which basically turns much of the FPGA into a dummy load. I use it for validating my power supply designs on my boards that have FPGAs. I can get it to periodically gate the clock to investigate the response of the power supply to load current steps.

The advantage of using the actual FPGA as the load (rather than a separate power supply tester / dummy load) is that it tests the actual component that matters. The only test equipment I need is a scope to look at the voltages.

It's not too hard to get under 20mV total voltage variation (transient + resitive drop + load regulation) from a fast 5A step. It can't be done without a few chunky Al-poly caps to handle the low frequencies though, at least not for the DC/DC converters I use.

[OT] I did have a surprise a few years ago when an FPGA design drawing about 15A caused too much voltage drop across a part of a plane due to the sheet resistance (about an ohm per square on an inner layer).

Adding a large fill on an outer layer in parallel with that plane fixed the problem on a subsequent revision of the design.

Regards, Allan

We did one test design that clocked every flop on a Cyclone chip at 250 MHz, just to satisfy our customer that we had enough power and cooling for any conceivable expansion.

Banging the clock on and off is a good idea, to test the low-frequency response of the power supplies.

On older Xilinx FPGAs that had internal tri-state busses, the "right" config file could blow up a chip.

Agree. The next thing to add (which we sometimes do) is some convenient coax connectors, SMBs or some such, to tap into the ground/power planes. It's hard to get an honest eval of plane noise with a scope probe.

Scope probes suck, mostly.

Right. Alum polymers are awesome.

15 AMPS?!!!

--

John Larkin                  Highland Technology Inc 
www.highlandtechnology.com   jlarkin at highlandtechnology dot com    

Precision electronic instrumentation 
Picosecond-resolution Digital Delay and Pulse generators 
Custom timing and laser controllers 
Photonics and fiberoptic TTL data links 
VME  analog, thermocouple, LVDT, synchro, tachometer 
Multichannel arbitrary waveform generators

rote:

te

t

Hz,

sponse

fig

oax

hard to

I believe a modern desktop cpu calls for something like 50A of core and 8A of IO supply at ~1V

-Lasse

response

to

The original PPC970MP sucked down about 100A at ~1.25V. Mobile CPUs are around 35W at about 1V, so 50A for a desktop CPU isn't outrageous.