USB Data Line Pullup

I'm discussing the data line pullup on a USB dev with someone and I'm not clear on one thing... or maybe two. The pullup is added to one or the other of the two differential data lines to indicate the speed of the interface being either low or full. This pullup is supposed to be

1.5 kohms to 3.3 volts. Once the pullup is detected is there any need to remove it? It does create a slight imbalance although that would be very small. I know some USB chips control this through a pin, but all that I have seen are either high speed or OTG controllers.

How exactly is the presence of the pullup detected? I can see telling if one or the other is present by the polarity of the bias on the D lines. But if no pullup is present the host has to know that. I suppose the differential pair is also read separately as a pair of single ended inputs to detect the three combinations?

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Rick C
Reply to
rickman
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Let's start with the easy question first. When a device is attached during an Idle state the hub or host senses which data line is more positive. The more positive line indicates the presence of a pull-up on that line.

What happens next is ambiguous to me. There are two cases: High Speed and Low / Full Speed.

High Speed

In the Idle state the pull-up resistance min-max is 900-1575 ohms. In the Active state the pull-up resistance min-max is 1425-3090 ohms. So does this mean that a permanent pull-up resistance of 1425-1575 ohms can be left in the circuit at all times?

Low / Full Speed.

Although nothing in writing says to remove the pull-up, schematics definitely show a pull-up enable circuit. All of my information in this follow up comes out of _USB Complete_ (Axelson).

Thank you,

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Don Kuenz KB7RPU
Reply to
Don Kuenz

Sure ;-) Just like tying a CMOS input to mid-supply >:-}

Maybe not so "complete" ?? ...Jim Thompson

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| James E.Thompson                                 |    mens     | 
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Reply to
Jim Thompson

Den tirsdag den 25. april 2017 kl. 19.05.07 UTC+2 skrev rickman:

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Reply to
Lasse Langwadt Christensen

I haven't seen the actual spec, but what I've read indicated the pull up was removed after the initial handshaking to use high speed. But this was just some web sites and they may have been over simplifying it or just wrong.

Maybe I don't quite understand. I thought IDLE state is a valid state even after the device has been detected. So what exactly is ACTIVE stage? In the reference Lasse gives they don't seem to mention ACTIVE as a state.

There's the rub. I don't trust the schematics. 99% of the drawings I find show a permanent pull up on a data line. But they may or may not be indicating an actual schematic vs. a conceptual drawing.

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Rick C
Reply to
rickman

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Reply to
Lasse Langwadt Christensen

That's for high speed transmission. I was wondering about full speed and low speed.

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Rick C
Reply to
rickman

A lot (all?) of the 1.5Mb/s (low speed) and 12Mb/s (full speed) USB transceivers ICs have three receiver outputs: RCV, Vp and Vm, for that very purpose.

See for example:

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Regards, Allan

Reply to
Allan Herriman

Why not refer to the USB specifications themselves. All this is covered in exhaustive detail. The USB specs are freely downloadable.

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John

Reply to
jrwalliker

Reading the specification is something I do when I'm designing *my* products, however this was a reply to a post by rickman; pointing out the obvious (like using Google or a canonical source such as the specification) doesn't seem to help.

Regards, Allan

Reply to
Allan Herriman

That's a good catch. It is a conceptional schematic that just happens to be correct in this case.

The PIC16C745 contains a low-speed USB transceiver. The USB transceiver uses three pins Vusb, D+, and D-. A typical application connects Vusb to D- with a 1.5 K ohm resistor. The DEV_ATT bit in the USB Control Register inserts and removes the pull-up resistor:

DEV_ATT: Device Attach Enables the 3.3V output. 1 = When DEV_ATT is set, the VUSB pin will be driven with 3.3V (nominal) 0 = The VUSB pins (D+ and D-) will be in a high impedance state

D- is more positive than D+ in the Idle state of a low-speed segment. This implies that DEV_ATT is set when the Idle state is entered and reset when the Idle state is exited. IOW the pull-up resistor is activated and deactivated during a session to accommodate the protocol.

It makes sense to me. YMMV. :0)

Thank you,

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Don Kuenz KB7RPU
Reply to
Don Kuenz

Perhaps I'm not familiar enough with USB operation to understand what this means. But it is my understanding that the IDLE state is the default state of the bus when nothing is being transmitted by either end. So doesn't the pull up need to be there at all times? If the pull up is disabled when not in IDLE state, how does the USB device know when the IDLE state is exited so to turn off the pull up? Also, what would be the purpose of this?

Isn't the IDLE state exited by the first data bit being sent by the host? If it is needed to remove the pullup to provide signal integrity, how can detection of that first bit be reliable with the pull up turned on?

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Rick C
Reply to
rickman

An Idle state only occurs when a low- or full-speed device is first attached. A device enters the Connect state after it has been in the Idle state for at least 2.5 microseconds but no more than 2.0 milliseconds.

Thank you,

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Don Kuenz KB7RPU
Reply to
Don Kuenz

It turns out that the USB 1.1 spec uses the nomenclature "Idle state" and "Bus Idle state." My first sentence in the above paragraph needs to read: "A Bus Idle state only occurs when a low- or full-speed device is first attached."

Thank you,

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Don Kuenz KB7RPU
Reply to
Don Kuenz

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