Hi,
I am developing a USB Isolator module ( prototype), using a cpld the direction of data is detected and the corresponding uni directional lines are enabled, which pass through the isolator and reach the other end.
The issue is the skew between two D lines is coming around 1000ps, the rise and fall time of the isolator is 2ns.
In USB Spec 2.0 for low and full speed buffers the signals have to be matched +/- 20% to reduce RFI and skew.
The skew i am getting from my circuit is much higher than that. Will it result in loss of data ??
Thanks and Regards
Aravind S