Top ten (10) stupid pcb layout mistakes

Whatever. Turn if off or buy a tool where it can be turned off. It's less than useless.

That's not great for controlled impedances or for small features (dense parts that need small vias). I'm often forces to go to 1.2mm because it won't route on a 1.6mm board (no space for vias).

how do you propose to do flooding with out connecting to the net you are asking it to connect to?

I've done that, though the footprint should have keepouts to prevent this.

Yep. Cables and connectors are always a PITA. I resort to making paper models of boards and cables so this doesn't happen.

You do it based on the net. Automatic flooding is going to get you into as much trouble as autorouting.

Ok, Molex pin numbering KK series. Our foot prints are all reversed, but I believe Molex did change them sometime in the 90's (can't be sure)

Cheers

It's not an autorouter issue (we don't autoroute.) It's that if a via has net name GND and it passes through the ground plane, it will be connected to the plane. That will make a nasty ground loop which wrecks the 4-wire connection. The 0r jumper lets us change the net name so the vias aren't GND any more.

We don't autoroute, so I have no current examples. I have seen an autorouter take a trace on the grand tour of a board, just to cover a short distance. Or use a dozen double-via jumps to get over one trace that could be easily moved to another layer.

Autorouters don't have a place-and-route strategy. Engineers are better at that.

Do you mean spokes? We don't. We "flood over" all vias.

Making things from paper and tape and strings is fun. Like being back in 2nd grade.

I know that every possible pin 1-2-3 permutation of the SOT23 package has been used by someone. And likely every possible 4-pin SOT143 permutation. That can create interesting library issues.

Forty years ago, we used autorouters all the time. In fact, they're always used at the chip (and FPGA) level. Things are a lot more regular in these cases, though. Simulated annealing algorithms work well in these cases. My guess is that there are too many shapes in a typical board for it to work well, though CPU time is cheap.

Yup, though for things like that, we let the MEs make the mistakes with their 3D tools. They can get all the boards, components, and metal bits modeled, too.

We have a separate library footprint for every part number. Too many of such problems. Not to mention that even diodes can't get the pin numbering right.

How thick was the FR4 layer that failed? I used to think that the dielectric strength of that stuff was very high, but I am starting to doubt its long-term reliability at high voltage.

My medium was toothpicks.

That picture almost looks like the real thing. Can a hobbyist get foil-covered mylar that can be etched at home?

There's often Cu-clad Kapton on eBay. Mylar won't take hand-soldering, wher eas Kapton doesn't even notice.

Cheers

Phil Hobbs

Thanks! I was looking for that but couldn't remember enough details. Must be old, the first time I heard Analog Man was over 25 years ago at a client.

That one is just paper, printed on my cheap HP color printer. It's a model of a matched-impedance kapton and copper flex that interfaces to a Pockels cell element. I find it easier to visualize 3D things if I make them out of paper. My wife loves that one for some reason... calls it "adorable."

You can buy sheets of copperclad Kapton on ebay, fairly cheap.