Top ten (10) stupid pcb layout mistakes

I use a signal naming convention that, if followed, eliminates this particular problem. The convention goes something like "owner_description_type". Where the "owner" is the device that "owns" the interface. So something like UC_DEBUG_TXD (and is part of the UC_DEBUG_ASYNC bus) is the UC's debug transmit port. All signals that go between devices are named such (local signals may just be "owner_name").

Cute comment, John. Ha Ha. Do you have some examples? Some anecdotes? If so, please share them.

Yeah I use eagle, and I make sure I pass all the tests, Eagle warns me about a lot of stupid stuff, Cad is great that way.

George H.

I usually label them SERIAL_FROM_blah or SERIAL_TO_blah or something like that, where blah is the name of the module or assembly.

On Thu, 26 May 2016 18:13:16 +0100, Syd Rumpo Gave us:

Most boards have one or two grounds (power plane and sometimes a separate 'signal ground')

You only need one and all the other test points do not need one proximal to them. Given the short length scope probe return leads have on them though, I can see your point. But 'copious'?

On Thu, 26 May 2016 17:27:49 -0500, Tim Wescott Gave us:

The problem comes when you want to do something that the tool isn't smart enough to understand (because there aren't mechanisms in place to convey the necessary information to it).

E.g., supporting different stuffing options on the same board, "shorting" two signals together (because *you* know one of the sources won't be present); putting two parts in the same physical real-estate, etc.

..and 1KV or better to help corona.

How about high-volt holdoff on 1KV supply layer, but not on gnd or pwr plan es?

PMT supply boards in UV/VIS spectrometer all fail after a couple of years. The 1KV eats through the multilayer board, turning it to conductive char, where the 1KV traces cross the gnd plane. Here's a fix:

Heh, drill out one fault, and a couple of months later the next shorts out.

Not PCB, but ASIC layout, so $cost *= 10000

Primitive outline marked the metallisation layers, but not the internal structure. Autorouter though it was cute to run a signal track over a primitive, between two power strips. Unfortunately the internals of the primitive had vias from the power strips to other layers. These vias were wider than the strips, but weren't shown on the outline, so no DRC errors, but a nice short. Picked up by BIST on the first samples, 100% fail, much swearing.

Luckily the signal track a) fused cleanly between the points where it crossed the power lines, and b) was part of an outgoing data bus with parity, so we were able to re-generate it with some external logic to progress with other testing while waiting for the re-spin (blew the timing, but allowed confirmation that the rest of the functionality was correct).

Think we added some DRC on the fully flattened design as a result. And keep-outs on primitives for the autorouter.

I was the newbie who'd done the routing, so I remember it rather well. Miffed that I missed it, as I would have moved the track if I'd seen it, just because it looked untidy (and I'd done exactly that elsewhere where more manual routing was required).

Making 4-wire connections to ordinary 2-terminal resistors is interesting, especially if one of the nodes is a plane or pour. The layout software will often optimize out the 4-wire scheme. I've had to use a 0-ohm jumper to allow me to rename a trace from GND to GND_RTD or something so I could route it without PADS connecting it to the ground plane every chance it could get.

I did a 1400 volt board (pictured eleswhere in the thread) where I specified huge plane clearances around thru-hole parts and vias (30 mils) so that wouldn't happen. I'll have to wait a few years to see if it was enough.

I thought you didn't use autorouters? If you can't turn of that behavior, buy a decent tool.

I started using the above convention because the netlist collated nicely. A little more rigor forces the TX/RX sorts of errors to zero.

Bundling busses has kept the I2C cross-wiring to zero, as well. I used to cross SDA and SCL all the time, with OrCAD.

Den fredag den 27. maj 2016 kl. 18.58.19 UTC+2 skrev krw:

afaict it isn't autorouting, it is polygon pouring

-Lasse

What I usually do is use thicker circuit board (adds next to nothing in cost and long as it's one of their standard thicknesses) and move the ground plane to the bottom layer, then stitch it through where it switches layer, without thermal reliefs.

planes?

ars. The 1KV eats through the multilayer board, turning it to conductive char, where the 1KV traces cross the gnd plane. Here's a fix:

out.

who uses thermal reliefs for vias?

-Lasse

I've seen it happen. Therefore, I always spell that out in the layout guidelines of the module spec.

Don't get me started.

Jeroen Belleman